16 Mar, 2009
5 commits
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Update CHANEGLOG, fix minor coding style issue.
Signed-off-by: Wolfgang Denk
15 Mar, 2009
2 commits
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The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8
bank SDRAMs.Signed-off-by: Gerald Van Baren
Acked-by: Dave Liu
Signed-off-by: Kim Phillips -
This patch makes sure the correct mask is applied when setting
the encryption and I2C bus 0 clock in SCCR.
Failing to do so may lead to ENCCM being 0 in which case I2C bus 0
won't function.Signed-off-by: Norbert van Bolhuis
Signed-off-by: Kim Phillips
14 Mar, 2009
1 commit
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Read and store OMAP3 die ID in U-Boot environment.
Signed-off-by: Dirk Behme
13 Mar, 2009
2 commits
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Set a non-zero speed in the MII register so that MII commands will work.
Signed-off-by: Jon Smirl
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Signed-off-by: Yusuke Goda
Signed-off-by: Nobuhiro Iwamatsu
12 Mar, 2009
8 commits
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The rtl8139 driver use pci_mem_to_phys. So it need PCI system memory
registration.Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Nobuhiro Iwamatsu -
Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu -
We can built 'make sh7785lcr_32bit_config'. And add new command "pmb"
for this mode. This command changes PMB for using 512MB system memory.Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Nobuhiro Iwamatsu -
Some register value was hardcoded for System memory size 128MB and
memory offset 0x08000000. This patch fixed the problem.Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Nobuhiro Iwamatsu -
It is necessary for some pci device driver.
Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Nobuhiro Iwamatsu -
Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Nobuhiro Iwamatsu -
Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Nobuhiro Iwamatsu -
Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu
11 Mar, 2009
2 commits
10 Mar, 2009
5 commits
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Commit af1c2b84 added a generic phy support, with an ID of zero
and a 32 bit mask; meaning that it will match on any PHY ID.The problem is that there is a test that checked if a matching
PHY was found, and if not, it printed the non-matching ID.
But since there will always be a match (on the generic PHY,
worst case), this test will never trip.In the case of a misconfigured PHY address, or of a PHY that
isn't explicitly supported outside of the generic support,
you will never see the ID of 0xffffffff, or the ID of the
real (but unsupported) chip. It will silently fall through
onto the generic support.This change makes that test useful again, and ensures that
the selection of generic PHY support doesn't happen without
some sort of notice. It also makes it explicitly clear that
the generic PHY must be last in the PHY table.Signed-off-by: Paul Gortmaker
Acked-by: Andy Fleming -
Fix typo in makefile which broke out of tree builds.
Also use expolicit "rm" instead of "ln -sf" which is known to be
unreliable.Signed-off-by: Wolfgang Denk
Signed-off-by: Kim Phillips -
This adds tsec12ioovcr to include/asm-ppc/immap_85xx.h (was reserved.)
Signed-off-by: Sergey Kubushyn
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These were left in accidentally, and are not really useful unless the
code is as broken as it was when it was being developed.Signed-off-by: Andy Fleming
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Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other
sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set.Signed-off-by: Ed Swarthout
09 Mar, 2009
3 commits
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
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Fix typo in makefile which broke out of tree builds.
Also use expolicit "rm" instead of "ln -sf" which is known to be
unreliable.Signed-off-by: Wolfgang Denk
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Conflicts:
lib_ppc/board.cSigned-off-by: Wolfgang Denk
06 Mar, 2009
10 commits
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add CONFIG_BOOTCOUNT_LIMIT feature for 8360 CPU.
The bootcounter uses 8 bytes from the muram,
because no other memory was found on this
CPU for the bootcount feature. So we must
correct the muram size in DTS before booting
Linux.This feature is actual only implemented for
MPC8360, because not all 83xx CPU have qe,
and therefore no muram, which this feature
uses.Signed-off-by: Heiko Schocher
Signed-off-by: Kim Phillips -
old code implemented the QE_ENET10 errata only for Silicon
Revision 2.0. New code reads now the Silicon Revision
register and sets dependend on the Silicon Revision the
values as advised in the QE_ENET10 errata.Signed-off-by: Heiko Schocher
Signed-off-by: Kim Phillips -
- HRCW update
HRCWH_BOOTSEQ_DISABLE not HRCWH_BOOTSEQ_NORMAL
HRCWH_LALE_EARLY added
- DDR-SDRAM settings modified. This solves sporadically
problems with this memory.
- CS1 now 128 MB window size
- CS3 now 512 MB window size
- PRAM activated
- MTDPARTS_DEFAULT defined
- CONFIG_HOSTNAME added
- MONITOR_LEN now 384 KBSigned-off-by: Heiko Schocher
Signed-off-by: Kim Phillips -
it is possible that some board variants have different DDR II
RAM sizes. So we autodetect the size of the assembled RAM.Signed-off-by: Heiko Schocher
Signed-off-by: Kim Phillips -
This patch adds I2C mux support for the fsl_i2c driver. This
allows you to add "new" i2c busses, which are reached over
i2c muxes. For more infos, please look in the README and
search for CONFIG_I2C_MUX.Signed-off-by: Heiko Schocher
Signed-off-by: Kim Phillips -
This patch adds I2C support for the Keymile kmeter1 board.
It uses the First I2C Controller from the CPU, for
accessing 4 temperature sensors, an eeprom with IVM data
and the booteeprom over a pca9547 mux.Signed-off-by: Heiko Schocher
Signed-off-by: Kim Phillips -
In case where a board not uses CONFIG_POST, it is not
necessary to init the DTTs when running from flash.Signed-off-by: Heiko Schocher
Signed-off-by: Kim Phillips -
1. RD_TO_PRE missed to add the AL, and need min 2 clocks for
tRTP according to DDR2 JEDEC spec.
2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec.
3. add the support of DDR2-533,667,800 DIMMs
4. cpo
5. make the AL to min to gain better performance.The Micron MT9HTF6472CHY-667D1 DIMMs test passed on
MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate.items 1, 2 and 5:
Acked-by: Joakim TjernlundReported-by: Joakim Tjernlund
Signed-off-by: Dave Liu
Signed-off-by: Kim Phillips -
The previous version rebooted forever with DDR bigger than 256MB.
Access the DS1339 RTC chip is on I2C1 bus.
Allow DHCP.Signed-off-by: Valeriy Glushkov
Signed-off-by: Kim Phillips -
The SerDes initialization should be finished before negating the reset
signal according to the reference manual. This isn't an issue on real
hardware, but we'd better stick to the specifications anyway.Suggested-by: Liu Dave
Signed-off-by: Anton Vorontsov
Signed-off-by: Kim Phillips
02 Mar, 2009
1 commit
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it is not necessary to init the DTTs so early,
so move this init to board_init_r ().Signed-off-by: Heiko Schocher
26 Feb, 2009
1 commit
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Fix following warning while compilation for mcc200 board:
lcd.c: In function 'lcd_display_bitmap':
lcd.c:625: warning: unused variable 'cmap'Signed-off-by: Anatolij Gustschin
