01 Apr, 2015
15 commits
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Signed-off-by: Tom Rini
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Create a new configuration file: at91-sama5_common.h. Which includes the
configurations that reused by all SAMA5 chips.at91-sama5_common.h includes:
- hw macros (clock, text_base and etc.)
- default commands.
- BOOTARGS
- U-Boot common configs.
NOTE: NOR flash definition should be put before including the common header.For sama5d3-xplained:
- add CMD_SETEXPRFor sama5d3xek:
- add CMD_SETEXPR
- change CONFIG_SYS_MALLOC_LEN to (4*1024*1024)Signed-off-by: Josh Wu
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Enable SPL support for at91sam9n12ek boards, now it supports
boot up from NAND flash, serial flash.Signed-off-by: Bo Shen
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Enable SPL support for at91sam9x5ek board. Now, it supports
boot up from NAND flash and SPI flash.Signed-off-by: Bo Shen
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Supports boot up from NAND flash with software ECC eanbled.
And supports boot up from SD/MMC card with FAT file system.As the boot from SD/MMC card with FAT file system, the BSS
segment is too big to fit into SRAM, so, use the lds to put
it into SDRAM.Signed-off-by: Bo Shen
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Config MCKR according to the datasheet sequence, or else it
will cause the MCKR configuration failed.Remove timeout checking for clock configuration, if configure
the clock failed, let the system hang while not run in wrong
clock configuration.Signed-off-by: Bo Shen
Tested-by: Heiko Schocher -
Insteading in mmc's raw sectors, this patch will save the environment
in a fat file (uboot.env) in mmc card's first FAT patition by default.If you want to save in mmc's raw sectors, you only need to define
CONFIG_ENV_IS_IN_MMC.Signed-off-by: Josh Wu
Acked-by: Bo Shen -
Add support for on-flash bad block table. This makes U-Boot handle an existing
BBT correctly.Signed-off-by: David Dueck
Reviewed-by: Boris BREZILLON
CC: Boris BREZILLON
CC: Josh Wu
CC: Andreas Bießmann
CC: Scott Wood
Acked-by: Josh Wu -
move MACH_TYPE into defconfig
Signed-off-by: Heiko Schocher
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To facilitate changing lowlevel_init to become s_init, move the current
contents of s_init into board_init_f and add the rest of what
board_init_f does here.
In order to compile clean without CONFIG_SKIP_LOWLEVEL_INIT set, leave an
empty stub of s_init(). It can be removed when lowlevel_init becomes s_init.Cc: Bo Shen
Cc: Andreas Bießmann
Tested-by: Matt Porter on sama5d3_xplained
Signed-off-by: Tom Rini
[rebased on current master, leave s_init() as empty stub]
Signed-off-by: Andreas Bießmann -
The commit 8dfafdd (Introduce common timer functions), add common
timer functions, we can use them directly.Signed-off-by: Bo Shen
[rebase on current master]
Sigend-off-by: Andreas Bießmann -
Signed-off-by: Bo Shen
[rebase on current master]
Signed-off-by: Andreas Bießmann -
This patch will display the U-Boot version on LCD.
Signed-off-by: Josh Wu
Acked-by: Bo Shen
31 Mar, 2015
12 commits
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Testing showed, that commands like STATUS made the buffer dirty
when executed with NFC_SECSZ set to the page size. It looks
like the controller transfers bogus data when this register
is configured. When setting it to 0, the buffer does not get
altered while the status command still seems to work flawless.Signed-off-by: Stefan Agner
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The driver tries to re-use the page buffer by storing the page
number of the current page in the buffer. The page is only read
if the requested page number is not currently in the buffer. When
a block is erased, the page number is marked as invalid if the
erased page equals the one currently in the cache. However, since
a erase block consists of multiple pages, also other page numbers
could be affected.The commands to reproduce this issue (on a written page):
> nand dump 0x800
> nand erase 0x0 0x20000
> nand dump 0x800The second nand dump command returns the data from the buffer,
while in fact the page is erased (0xff).Avoid the hassle to calculate whether the page is affected or not,
but set the page buffer unconditionally to invalid instead.Signed-off-by: Stefan Agner
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This command is only enabled by one board, complicates the NAND code,
and doesn't appear to have been functioning properly for several
years. If there are no bad blocks in the NAND region being written
nand_write_skip_bad() will take the shortcut of calling nand_write()
which bypasses the special yaffs handling. This causes invalid YAFFS
data to be written. See
http://lists.denx.de/pipermail/u-boot/2011-September/102830.html for
an example and a potential workaround.U-Boot still retains the ability to mount and access YAFFS partitions
via CONFIG_YAFFS2.Signed-off-by: Peter Tyser
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The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some
time and a more generic method of NAND verification now exists in U-Boot.Signed-off-by: Peter Tyser
Tested-by: Heiko Schocher
Acked-by: Heiko Schocher -
Previously NAND writes were not verified and could fail silently. Add
a verification step after all writes to NAND.Signed-off-by: Peter Tyser
Reviewed-by: Lukasz Majewski
Tested-by: Heiko Schocher
Acked-by: Heiko Schocher -
Previously NAND writes were only verified when CONFIG_MTD_NAND_VERIFY_WRITE
was defined. On boards without this define writes could fail silently.
Boards with CONFIG_MTD_NAND_VERIFY_WRITE could prematurely report
failures which ECC could correct.Add a verification step after all "nand write[.x]" commands to ensure the
writes were successful. The verification uses ECC for for "normal"
writes, but does not for raw and yaffs writes. Some test cases which
inject fake bad bits on a 2K page flash are below.Test cases with CONFIG_MTD_NAND_VERIFY_WRITE defined:
Example of an ECC write which previously failed when
CONFIG_MTD_NAND_VERIFY_WRITE was defined, but now succeeds because ECC
is used during verification:
nand erase 0 0x10000
dhcp /somefile
mw.b 0x10000 0xff 0x2000
mw.b 0x10020 0xfe 1
nand write.raw 0x10000 0x800 1
mw.b 0x1000020 0x01 1
nand write 0x1000000 0x800 0x1800Test cases without CONFIG_MTD_NAND_VERIFY_WRITE defined:
Example of an ECC write which previously silently failed:
nand erase 0 0x10000
dhcp /somefile
mw.b 0x10000 0xff 0x2000
mw.b 0x10020 0x00 1
nand write.raw 0x10000 0x800 1
mw.b 0x1000020 0xff 1
nand write 0x1000000 0x800 0x1800Example of a raw write which previously failed silently due to stuck
data bit, but now errors out:
nand erase 0 0x10000
dhcp /somefile
mw.b 0x10000 0xff 0x2000
mw.b 0x10020 0xfe 1
nand write.raw 0x10000 0x800 1
mw.b 0x1000020 0x01 1
nand write.raw 0x1000000 0x800 3Example of a raw write which previously failed silently due to stuck OOB
bit, but now errors out:
nand erase 0 0x10000
dhcp /somefile
mw.b 0x10000 0xff 0x2000
mw.b 0x10810 0xfe 1
nand write.raw 0x10000 0x800 1
mw.b 0x1000810 0x01 1
nand write.raw 0x1000000 0x800 3Signed-off-by: Peter Tyser
Tested-by: Heiko Schocher
Acked-by: Heiko Schocher -
Add nand_verify() and nand_verify_page_oob(). nand_verify() verifies
NAND contents against an arbitrarily sized buffer using ECC while
nand_verify_page_oob() verifies a NAND page's contents and OOB.Signed-off-by: Peter Tyser
Tested-by: Heiko Schocher
Acked-by: Heiko Schocher -
The use of the nand_write_options and nand_read_options structures were
removed in commit dfbf617ff055e4216f78d358b0867c548916d14b. Remove the
now-unused structures too.Signed-off-by: Peter Tyser
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This option was removed along with legacy NAND support in
be33b046b549ad88c204c209508cd7657232ffbd. Clean up some remnants.Signed-off-by: Peter Tyser
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There is only one pio_word in this DMA transaction so data field must be 1.
Signed-off-by: Luca Ellero
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There is only one pio_word in this DMA transaction so data field must be 1.
Signed-off-by: Luca Ellero
30 Mar, 2015
7 commits
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By specification the FIFO size would be in a range 2-256 bytes. From TX Level
prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes.
Hence there are currently two issues:
a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be
either 0 or 1 byte;
b) FIFO size is incorrectly decreased by 1 which already done by meaning of
TX Level register.Fixes: 501943696ea4 (spi: designware_spi: Fix detecting FIFO depth)
Signed-off-by: Andy Shevchenko
Signed-off-by: Axel Lin
Acked-by: Pavel Machek
Reviewed-by: Jagannadha Sutradharudu Teki -
Make local functions static and remove unneeded forward declarations.
Signed-off-by: Axel Lin
Reviewed-by: Jagannadha Sutradharudu Teki -
Don't assume slave is always the first member of struct cf_spi_slave.
Use container_of instead of casting first structure member.Signed-off-by: Axel Lin
Reviewed-by: Jagannadha Sutradharudu Teki -
This patch enables QUAD read mode for qspi to improve the
read performace while loading the binaries from qspi.Signed-off-by: Ravi Babu
Reviewed-by: Jagannadha Sutradharudu Teki -
Don't assume slave is always the first member of struct ftssp010_spi.
Use to_ftssp010_spi() to ensure free correct address in spi_free_slave().Signed-off-by: Axel Lin
Reviewed-by: Jagannadha Sutradharudu Teki -
It's done in spi_alloc_slave().
Signed-off-by: Axel Lin
Reviewed-by: Jagannadha Sutradharudu Teki -
The third parameter of container_of is the name of the member within the struct.
Current code only works if the parameter passed to to_cf_qspi_slave named slave.
Fix it.Signed-off-by: Axel Lin
Reviewed-by: Jagannadha Sutradharudu Teki
29 Mar, 2015
6 commits
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Signed-off-by: Hans de Goede
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following kernel patches to reduce the cpu clock to 912MHz due to
reported instability at 1008MHz, select 912MHz as the boot speed
for the a10-limeSigned-off-by: Iain Paton
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
make the CPU clock selectable via Kconfig
this removes the sunxi specific CONFIG_CLK_FULL_SPEED defined in each
soc header and replaces it's use in board/sunxi/board.c with
CONFIG_SYS_CLK_FREQ from Kconfig which allows us to configure board
specific frequency on bootSigned-off-by: Iain Paton
[hdegoede@redhat.com s/CONFIG_SYS_CLK_FREQ/CONFIG_TIMER_CLK_FREQ/ for the
arch-timer clk speed on sun7i to fix mis-compile on sun7i]
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
clock_set_pll1 would pick the next highest available cpu clock speed if
a value not in the pre defined table was selected. this potentially
results in overclocking the soc.reverse the selection method so that we select the next lowest speed
and add the missing 912Mhz setting that's requested by sun7i which also
uses the sun4i clock code.Signed-off-by: Iain Paton
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
The usb0 / otg phy on sunxi boards has a bug where it wrongly detects a
high speed squelch on usb reset deassert when a lo speed device is plugged in.The android kernel has a work around for this in the form of temporary
disabling the phy's squelch detection on reset deassert, this commit adds
the same workaround to the u-boot sunxi musb code, thereby fixing various usb
lo speed devices not working.Tested with a (before non working) usb keyboard and a usb 2.4 GHz wireless
keyboard/mouse combo receiver.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
Add CONFIG_SYS_GENERIC_BOARD to amcc-common.h and CONFIG_DISPLAY_BOARDINFO
to Kconfig files. canyonlands.h includes amcc-common.h, so remove
CONFIG_SYS_GENERIC_BOARD definition there.Signed-off-by: Anatolij Gustschin
Cc: Stefan Roese
Cc: Feng Kan
Cc: Masahiro Yamada
Cc: Tom Rini
