20 Jul, 2016
1 commit
05 May, 2016
1 commit
26 Apr, 2016
2 commits
14 Jan, 2016
2 commits
08 Jan, 2016
1 commit
07 Jan, 2016
1 commit
14 Nov, 2015
1 commit
16 Sep, 2015
2 commits
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The WAKEUP_X pins are always an input no matter the pinmux mode.
However, the 18th bit that typical configures a pin as an input is
considered reserved for the WAKEUP_X pins. Therefore, for any WAKEUP
pin remove any configuration that sets that pin as an input. Since
those pins are only inputs remove any output configuration from those
pins.Signed-off-by: Franklin S Cooper Jr
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This reverts commit b5a8694cf6a0f2ac504e16e3068b967f3ecc8700.
This patch was incorrectly setting the 18th bit of the padconf register
which is reserved.
11 Sep, 2015
1 commit
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WAKEUP2 is used as a gpio input for the touch screen controller's interrupt
output signal. It was incorrect to set it as an output in the first place.This is valid for both the OSD panel that uses the EDT FT5506 touchscreen
controller and the LG panel that uses the LDC3001 touchscreen controller.Signed-off-by: Franklin S Cooper Jr
Signed-off-by: Dan Murphy
09 Sep, 2015
5 commits
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CONFIG_SPL_NET_VCI_STRING is available only with BOOTP. So if
CMD_DHCP is enabled for SPL in usb ether boot, it will not pass
the right vendor name and failing to download the right file.
Also all the net CMD_* are not required in SPL builds. So defining
these only for non-SPL builds.Reported-by: Yan Liu
Signed-off-by: Lokesh Vutla
Reviewed-by: Sekhar Nori -
securedb.key.bin is not supported so it should not be loaded by
default init_ubi command.Signed-off-by: Carlos Hernandez
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UBI images created by OE does not contain boot partition by default,
instead kernel and dtb are placed in /boot directory inside rootfs
partition. So update env commands to load files from correct
location.Signed-off-by: Carlos Hernandez
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commit 319a9963e68a ("am43xx: Add USB device boot support to SPL")
tries to disable env for for SPL with CONFIG_SPL_USBETH_SUPPORT but
it also disables env for all non SPL builds.
Fix it by disabling env for SPL with CONFIG_SPL_USBETH_SUPPORT.Signed-off-by: Lokesh Vutla
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Currently when phy device is created the link variable is
initialized to 1 which denoted phy link is already up. On a power
reset there is no issue as phy status register link status will
not be set, so phy auto negotiate will be started. But when a cpu
reset is issued (ex: dra72x-evm) phy's link status bit is already
set which leads to assume that link is already setup in
genphy_update_link() initial check which results in ehternet not
working. So do not assume that link is already up and on phy
device create set link to zero. This is verified on dra72x-evm.Reported-by: Franklin S Cooper Jr
Signed-off-by: Mugunthan V N
Acked-by: Joe Hershberger
02 Sep, 2015
5 commits
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All the rtc_only related functions are not needed for the second stage
of the bootloader hence pushing all the code under LOWLEVEL_INIT macro.This fixes compile time warning when built with am335x_evm_defconfig.
Signed-off-by: Keerthy -
- Re-org env sections so that we can fall back to env is in FAT on SD
card, for broader board compatibility
- Add am335x_evm_nandboot as example of NAND envThis is for the TI integration tree only as the plan for upstream is to
work towards env location being selectable via KconfigSigned-off-by: Tom Rini
Signed-off-by: Lokesh Vutla -
If EMIF is idle for certain amount of DDR cycles, EMIF will put the
DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register
is programmed. And also before entering suspend-resume ddr needs to
be put in self-refresh. Linux kernel does not program this register
before entering suspend and relies on u-boot setting.
So configuring it in u-boot.Signed-off-by: Nishanth Menon
Signed-off-by: Lokesh Vutla -
On DRA7, refresh ctrl shadow should be updated with
the final value.Signed-off-by: Lokesh Vutla
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Weak versions of board_usb_init and board_usb_cleanup are defined in common USB
host code, but it is also used for USB device gadgets, so we also need a weak
definition of it when there is no USB host enabled.
Both weak definitions do not conflict.Tested-by: Lukasz Majewski
Signed-off-by: Paul Kocialkowski
Signed-off-by: Lokesh Vutla
28 Aug, 2015
2 commits
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clrsetbits_le32/clrbits_le32 takes mask of the bits as input that
are needed to be set/clear. But emif driver passes the shift of the bits.
Fixing it here.Reported-by: Mark Mckeown
Signed-off-by: Lokesh Vutla -
With commit aee119bd70b8 ('am43xx_evm: add usb host boot support') usb
commands is removed from U-boot second stage and enbaled only on USB
boot config. Fixing this by enable USB commands for both USB boot and
in second stage u-boot.Signed-off-by: Mugunthan V N
27 Aug, 2015
3 commits
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Linux kernel can enumerate mmc sd as either mmcblk0 or mmcblk1.
But u-boot default environment assumes that sd always populates
as mmcblk0. With this the root fs is not being mounted when
mmc sd is enumerated as mmcblk1.
So use partuuid to update root= option in default environment.Reported-by: Yan Liu
Signed-off-by: Lokesh Vutla -
Define default mmc args in ti_armv7_common.h so that all
TI platforms can reuse.Reported-by: Yan Liu
Signed-off-by: Lokesh Vutla -
All TI SoCs expect filesystem to be ext4, omap4_common is the only one
with ext3. move omap4 to ext4 so that we can start consolidating MMC
arguments.Signed-off-by: Lokesh Vutla
25 Aug, 2015
1 commit
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Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag,
instead of platform.Acked-by: Vignesh R
Signed-off-by: Vishal Mahaveer
21 Aug, 2015
3 commits
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DRA72x processor variants are single core and it does not export ACP[1].
Hence, we have no source for generating an external snoop requests which
appear to be key to the deadlock in DRA72x design.Since we build the same image for DRA74x and DRA72x platforms, lets
runtime detect and disable the workaround (in favor of performance) on
DRA72x platforms.[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html
Suggested-by: Richard Woodruff
Suggested-by: Brad Griffis
Reviewed-by: Brad Griffis
Signed-off-by: Nishanth Menon
(cherry picked from commit 095a5ef88e08c3df0f273c20a39cb921900cfae6)
Signed-off-by: Dan Murphy -
Implement logic for ACR(Auxiliary Control Register) configuration using
ROM Code smc service.Suggested-by: Richard Woodruff
Suggested-by: Brad Griffis
Reviewed-by: Brad Griffis
Signed-off-by: Nishanth Menon
(cherry picked from commit 1bbb556a6a5c0f44d2da32700fce4d279c851e9f)
Signed-off-by: Dan Murphy -
Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
that "A livelock can occur in the L2 cache arbitration that might
prevent a snoop from completing. Under certain conditions this can
cause the system to deadlock. "Recommended workaround is as follows:
Do both of the following:1) Do not use the write-back no-allocate memory type.
2) Do not issue write-back cacheable stores at any time when the cache
is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
is implementation defined whether cacheable stores update the cache when
the cache is disabled it is not expected that any portable code will
execute cacheable stores when the cache is disabled.For implementations of Cortex-A15 configured without the “L2 arbitration
register slice” option (typically one or two core systems), you must
also do the following:3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111
So, we provide an option to disable write streaming on OMAP5 and DRA7.
It is a rare condition to occur and may be enabled selectively based
on platform acceptance of risk.Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
is set to 0.Note: certain unicore SoCs *might* not have REVIDR[3] not set, but
might not meet the condition for the erratum to occur when they donot
have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
Extensions). Such SoCs will need the work around handled in the SoC
specific manner, since there is no ARM generic manner to detect such
configurations.Based on ARM errata Document revision 18.0 (22 Nov 2013)
Suggested-by: Richard Woodruff
Suggested-by: Brad Griffis
Reviewed-by: Brad Griffis
Signed-off-by: Nishanth Menon
(cherry picked from commit a615d0be6a73fc48a22e5662608260fe9b9149ff)
Signed-off-by: Dan Murphy
14 Aug, 2015
3 commits
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CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE is dropped in the driver as
it is required for all the platforms, so dropping the same from
config file alsoSigned-off-by: Mugunthan V N
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phy_find_by_mask() is not used by any of the platform which uses
keystone_net driver, so removing the unused code.Signed-off-by: Mugunthan V N
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Update env to load images from mmc.
Reported-by: Nishanth Menon
Signed-off-by: Lokesh Vutla
13 Aug, 2015
4 commits
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The default boot command searches for dofastboot varaiable
and does a fastboot if it is set to 1.
But the condition "if test ${dofastboot} -eq 1" always
returns true if dofastboot is not defined and breaking mmc boot.
So make dofastboot as 0 by default and let the runtime
environment set it if fastboot is required.Signed-off-by: Lokesh Vutla
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DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet
provided IODELAY values for standard RGMII phys do not work.Silicon Revision(SR) 2.0 provides an alternative bit configuration
that allows us to do a "gross adjustment" to launch the data off a
different internal clock edge. Manual IO Delay overrides are still
necessary to fine tune the clock-to-data delays. This is a necessary
workaround for the quirky ethernet Phy we have on the platform.NOTE: SMA registers are spare "kitchen sink" registers that does
contain bits for other workaround as necessary as well. Hence the
control for the same is introduced in a generic SoC specific, board
generic location.Signed-off-by: Nishanth Menon
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Silicon revision 2.0 has new signal routing hence has an updated set of
iodelay parameters to be used. Update the configuration for the same.
Padmux remains the same.Based on data from VayuES2_EVM_Base_Config-20150807.
NOTE: With respect to the RGMII values, the Manual IODelay values
are used for the fine adjusments needed to meet the tight RGMII
specification.Signed-off-by: Nishanth Menon
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For am43xx_rtconly_evm_defconfig, the bootloader indicates support for
RTC-Only modes by writing a magic number into RTC scratch register
which kernel PM code will then clear and then write back again if
RTC-Only mode entry is desired. If no PM code is loaded in the kernel,
this magic number will not get cleared and then be detected again
by the bootloader on a warm reboot, indicating an RTC+DDR resume event
and causing the bootloader to attempt to jump to the resume address in
RTC scratch register 0, which is invalid.Add a check to prevent jumping to address 0 if the scratch register is
not properly programmed, otherwise warm reboot will not work on am437x
if no PM is loaded in the kernel.Signed-off-by: Dave Gerlach
12 Aug, 2015
2 commits
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ARM supported speeds and init value of core_pll for SDP1200
are programmed wrong as part for the device speed cleanups.
Fixing it here.Signed-off-by: Lokesh Vutla
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On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov "
and based on the previous work done by "Hao Zhang "Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov
Tested-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla