05 May, 2014
1 commit
-
Structure definition used type block_dev_desc_t, defined in part.h, which
wasn't included in mmc.h. It worked only in circumstances when common.h,
or another header using part.h was incuded in implementation files.Change-Id: I5b203928b689887e3e78beb00a378955e0553eb7
Signed-off-by: Mateusz Zalega
Acked-by: Pantelis Antoniou
Cc: Minkyu Kang
29 Apr, 2014
1 commit
-
This driver needs a data structure in SRAM before SDRAM is available.
This is not alway the case using .data section. Moving this data
structure to global_data guarantees it is writable.Signed-off-by: York Sun
CC: Troy Kisky
26 Apr, 2014
3 commits
25 Apr, 2014
2 commits
-
Signed-off-by: Alexey Brodkin
-
With 32 milliseconds delay on some boards EEMPROM got written inconsistently.
With 64 msec all of our existig boards show properly written EEPROM.Cc: Tom Rini
Signed-off-by: Alexey Brodkin
24 Apr, 2014
1 commit
-
add support for the ids8313 board.
CPU: e300c3, MPC8313, Rev: 2.1 at 396 MHz, CSB: 132 MHz
I2C: ready
SPI: ready
DRAM: 128 MiB (DDR2, 32-bit, ECC off, 264 MHz)
Flash: 8 MiB
NAND: 128 MiB
Net: TSEC0, TSEC1 [PRIME]public key on NOR flash start
Signed-off-by: Heiko Schocher
Signed-off-by: Kim Phillips
23 Apr, 2014
32 commits
-
Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND boot, fix it.Signed-off-by: Shaohui Xie
Reviewed-by: York Sun -
- update readme.
- add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315
ucode from NOR/NAND/SPI/SD/REMOTE.
- update cpld vbank with SW3[5:7]=000 as default vbank0 instead of
previous SW3[5:7]=111 as default vbank.
- fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control
to u-boot.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers
control to u-boot.Signed-off-by: Shengzhou Liu
[York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH]
Reviewed-by: York Sun -
Adds support for clock sourcing from sysclk(100MHz) for usb
on T104xRDB and T1040QDS. This requires changing reference divisor
and multiplication factor to derive usb clock from sysclk.Signed-off-by: Nikhil Badola
Reviewed-by: York Sun -
T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode.
In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock
(100MHz) to the following PLLs:
• Platform PLL
• Core PLLs
• USB PLL
• DDR PLL, etcThe cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or
DIFF_SYSCLK (differential) is selected as the clock input to the chip.get_sys_info has been enhanced to add the diff_sysclk so that the
various drivers can be made aware of ths diff sysclk configuration and
act accordingly.Other changes:
-single_src to ddr_refclk_sel, as it is use for checking ddr reference clock
-Removed the print of single_src from get_sys_info as this will be
-printed whenever somebody calls get_sys_info which is not appropriate.
-Add print of single_src in checkcpu as it is called only once during initializationSigned-off-by: Poonam Aggrwal
Signed-off-by: Priyanka Jain
Signed-off-by: Vijay Rai
Reviewed-by: York Sun -
u-boot binary size for Freescale mpc8536DS platforms is 512KB.
This has been reached to upper limit of the platforms and causig
linker error. So increase the u-boot binary size to 768KB.Signed-off-by: Haijun Zhang
Reviewed-by: York Sun -
U-boot binary size has been increased from 512KB to 768KB.
So update CONFIG_SYS_MONITOR_LEN to reflect the same.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordinglySigned-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Add support of 2 stage NAND boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordinglySigned-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Add support of loading image, binary for MMC and SPI during SPL boot.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
T1042RDB_PI board does not have QE connector.
So disable CONFIG_QE and CONFIG_U_QE for T1042RDB_PI
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Add u-qe support for t1040qds
Signed-off-by: Zhao Qiang
Reviewed-by: York Sun -
Add deep sleep support on T104xRDB platforms.
Signed-off-by: Tang Yuantian
Reviewed-by: York Sun -
Add deep sleep support on T1040QDS platform.
Signed-off-by: Tang Yuantian
Reviewed-by: York Sun -
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun -
Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0.
This decreases data burst rate with which data packets are posted from the TX
latency FIFO to compensate for latencies in DDR pipeline during DMA.
This avoids Tx buffer underruns and leads to successful usb writesSigned-off-by: Ramneek Mehresh
Signed-off-by: Nikhil Badola
Reviewed-by: York Sun -
T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.
This support of CPLD includes
- files and register defintion
- Commands to swtich alternate bank and default bankSigned-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
T1040RDB, T1042RDB header files are very similar so merged into new header file T104xRDB.
T104xRDB header file can support both T1040RDB and T1042RDB_PI header.Patch makes following changes
-Update Boards.cfg file for T1040RDB and T1042RDB_PI
-Add new T104xRDB header file
-Delete T1040RDB, T1042RDB_PI header fileSigned-off-by: Vijay Rai
Signed-off-by: Priyanka Jain
Reviewed-by: York Sun -
NOR flash is on CS1 instead of CS2 when NAND boot.
So correct NOR chip selection to CS1 from CS2.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
T1040QDS_D4 is a variant of T1040QDS, with additional circuit to support
DDR4 memory. Tested with MTA9ASF51272AZ-2G1AYESZG.Signed-off-by: York Sun
-
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.Signed-off-by: York Sun
-
For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address
within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded
to higher address to support large space.Signed-off-by: York Sun
CC: Prabhakar Kushwaha -
add CONFIG_QE, CONFIG_U_QE and CONFIG_SYS_QE_FW_ADDR into
"include/configs/T1040RDB.h"Signed-off-by: Zhao Qiang
Reviewed-by: York Sun -
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.Signed-off-by: Zhao Qiang
Reviewed-by: York Sun -
In case of secure boot from NAND, the DDR is initialized by the
BootROM using the config words (CF_WORDS) in the CF_HEADER
and u-boot image is copied from NAND to DDR by the BootROM.
So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NANDSigned-off-by: Aneesh Bansal
Reviewed-by: York Sun -
Add NOR, SPI and SD secure boot targets for BSC9132QDS.
Changes:
- Debug TLB entry is not required for Secure Boot Target.Signed-off-by: Aneesh Bansal
Reviewed-by: York Sun -
The workaround for IFC errata A003399 was not enabled
in case of secure boot. So, secure boot from NOR was not
working.Signed-off-by: Aneesh Bansal
Reviewed-by: York Sun -
In case of secure boot from NAND, the DDR is initialized by the
BootROM using the config words (CF_WORDS) in the CF_HEADER
and u-boot image is copied from NAND to DDR by the BootROM.
So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND.Signed-off-by: Aneesh Bansal
Reviewed-by: York Sun
