Eric Lee / smarc-uboot

06 Aug, 2015

1 commit

04 Apr, 2015

1 commit

  • 48277f0a5   MLK-10496: Check the PL310 version for applying errata ... Browse Code »

    Apply errata based on PL310 version instead of compile
    time. Also set Prefetch offset to 15, since it improves
    memcpy performance by 35%. Don't enable Incr double
    Linefill enable since it adversely affects memcpy
    performance by about 32MB/s and reads by 90MB/s. Tested
    with 4K to 16MB sized src and dst aligned buffer.

    Signed-off-by: Nitin Garg

    Nitin Garg
     

01 Apr, 2015

1 commit

  • 8be05ef58   MLK-10524: iMX6x: Implement workaround for Cortex-A9 errata 845369 ... Browse Code »

    Under very rare timing circumstances, transitioning into streaming
    mode might create a data corruption. Present on Two or more processors
    or 1 core with ACP, all revisions. This erratum can be worked round
    by setting bit[22] of the undocumented Diagnostic Control Register to 1.

    Signed-off-by: Nitin Garg
    (cherry picked from commit 70ad44e523680de67dd8b7a7505d7f27799980ee)

    Nitin Garg
     

05 Mar, 2015

1 commit

  • 6baaad39a   MLK-10215 Add elan init in i.MX6SL-EVK board ... Browse Code »

    EPDC board contain a elan touch screen, this screen is a i2c
    slave. If this EPDC board connect to i.MX6SL-EVK board, after
    uboot boot up, if we do i2c operation, like i2c probe, then
    the i2c bus block. This is due to the elan touch screen i2c slave.
    This device needs to do some initialization opearation before its
    i2c operation, otherwise this i2c device pull down the i2c clk line,
    and make the i2c bus hang. This means elan needs a special flow on
    i2c before its address is acked, otherwise the i2c bus will be hang.

    This patch is a workaround, it add a void function which is defined
    as a weak symbol in i2c driver, and it is called before every i2c
    operation. In mx6slevk, this function was overwrite to execute elan
    initialization. So that, for mx6slevk board, it will initialize
    elan before every i2c operation, but for other boards, it just work
    as before.

    Signed-off-by: Haibo Chen

    Haibo Chen
     

18 Dec, 2014

1 commit

24 Nov, 2014

1 commit

  • 0168d205f   MLK-9898 imx:mx6 fix ana2 offset of fuse bank1 ... Browse Code »

    According to RM, there is 16bytes between offset ana1 and offset ana2.
    So should add 3 int hole 'u32 reserved[3]' between ana1 and ana2.

    Also add the reserved bytes for ana2 in this patch.

    Signed-off-by: Peng Fan
    (cherry picked from commit b0fd5f272895dfb0891872c099df7eef1519f729)

    Peng Fan
     

11 Nov, 2014

1 commit

  • b34b40e49   MLK-9819: ARM: mx6sx: clear WDOG3 Power Down Enable bit for i.mx6sx ... Browse Code »

    Since we use WDOG_B reset now, we have to clear WDOG3 Power Down Enable
    bit to avoid system reboot during normal kernel boot.
    For mx6sxsabresd board, we have to make sure pad setting for WDOG_B ready
    before mux ready, otherwise also cause reboot. But that dependes on hardware
    design, only need on mx6sxsabresd board.

    Signed-off-by: Robin Gong
    (cherry picked from commit 26875f93ac7e84748fa63e5f0dd948d12e663e43)

    Robin Gong
     

20 Oct, 2014

1 commit

30 Sep, 2014

1 commit

23 Sep, 2014

1 commit

18 Sep, 2014

5 commits

11 Sep, 2014

1 commit

10 Sep, 2014

1 commit

05 Sep, 2014

1 commit

  • aa76a7e47   ENGR00329484-2 ARM:MX6: Clear Align bit in SCTLR ... Browse Code »
    5

    This problem is found when debugging QuadSPI. When "A" bit is enabled,
    unaligned access will cause data abort exception. Actually, we do not
    want this exception. So clear the align bit for MX6 SOCs.

    Tested this code with android team colleague and did not find problem.

    Signed-off-by: Peng Fan

    Peng Fan
     

02 Sep, 2014

1 commit

30 Aug, 2014

1 commit

  • ac6272627   ENGR00323255 Fixed QSPI randomly access timeout issue ... Browse Code »

    The QSPI clock rate was set without disabling the clock gate, the
    randomly glitch may mess up the clock and there will be no clock output,
    when kernel boot up the QSPI access will fail.

    To debug this issueon i.MX6SX SDB, changed the u-boot bootscript to 'sf probe; reset'
    to keep rebooting, the issue can be reproduced in 20 mins, set clock out
    register in CCM and measured TP86, found there is no clock ouput.

    To fix this bug, disable clock gate before changing clock rate.
    NOTICE: QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, need
    to disable both of them.

    Signed-off-by: Allen Xu

    Allen Xu
     

26 Aug, 2014

2 commits

25 Aug, 2014

1 commit

  • 53118db42   ENGR00328312 i2c: imx: Optimize the i2c device recovery solution ... Browse Code »
    12

    From i2c spec, if device pull down the SDA line that causes
    i2c bus dead, host can send out 9 clock to let device release
    SDA.

    But for some special device like pfuze100, it pull down SDA line
    and the solution cannot take effort.

    The patch just add NACK and STOP signal after 8 dummy clock, and pmic
    can release SDA line after the recovery. Test case catch 375 times of
    i2c hang, and all are recovered.

    Signed-off-by: Fugang Duan

    Fugang Duan
     

15 Aug, 2014

1 commit

  • 01996acd7   ENGR00326994 iMX6: Checking PLL2 PFD0 and PFD2 for periph_clk before reset ... Browse Code »

    u-boot v2014 upstream codes have a problem in pfd reset (s_init function)
    that imx6 Dual is not applied for PLL2 PFD2 reset. It is originated by
    using dynamical cpu type checking and introducing two cpu types:
    MXC_CPU_MX6Q and MXC_CPU_MX6D for iMX6 Dual/Quad platform.

    Fixed this problem by checking the pre_periph_clk_sel and pre_periph2_clk
    of CCM CBCMR register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock
    source, do not reset this PFD to avoid system hang.

    Signed-off-by: Ye.Li

    Ye.Li
     

31 Jul, 2014

1 commit

  • ec78595a2   ENGR00325255 pcie:enable pcie support on imx6sx sd ... Browse Code »
    32

    Enable pcie support in uboot on imx6sx sd boards
    - enable_pcie_clock should be call before ssp_en is set,
    since that ssp_en control the phy_ref clk gate, turn on
    it after the source of the pcie clks are stable.
    - add debug info
    - add rx_eq of gpr12 on imx6sx
    - there are random link down issue on imx6sx. It's
    pcie ep reset issue.
    solution:reset ep, then retry link can fix it.

    Signed-off-by: Richard Zhu

    Richard Zhu
     

17 Jul, 2014

2 commits

15 Jul, 2014

2 commits

  • d7299ad75   MX6: Correct calculation of PLL_SYS ... Browse Code »

    DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do
    the shift after the multiply to avoid rounding errors

    Signed-off-by: Andre Renaud
    (cherry picked from commit 2eb268f6fd236a5ad9d51e7e47190d7994b3920f)

    Andre Renaud
     
  • a040e7960   mx6: soc: Update the comments of set_ldo_voltage() ... Browse Code »

    Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces
    set_ldo_voltage() function that can be used to set the voltages
    of any of the three LDO regulators controlled by the PMU_REG_CORE register.

    Prior to this commit there was a single set_vddsoc() which only configured the
    VDDSOC regulator.

    Update the comments to align with the new set_ldo_voltage() implementation.

    Acked-by: Jason Liu
    Signed-off-by: Fabio Estevam
    (cherry picked from commit 157f45da91b306d71dbf3a51325352dc11bf16d1)

    Fabio Estevam
     

07 Jul, 2014

1 commit

04 Jul, 2014

1 commit

30 Jun, 2014

1 commit

  • 987c48c07   ENGR00320350 iMX6SLEVK: Fix build warning of PCIE Phy power down ... Browse Code »
    5

    Since the iMX6SL does not have PCIE module, should not define the
    function "imx_set_pcie_phy_power_down" for it. Otherwise, get the
    build warning below:

    arch/arm/cpu/armv7/mx6/soc.c:446:13: warning: 'imx_set_pcie_phy_power_down'
    defined but not used [-Wunused-function]
    static void imx_set_pcie_phy_power_down(void)

    Signed-off-by: Ye.Li

    Ye.Li
     

25 Jun, 2014

1 commit

24 Jun, 2014

1 commit

  • 5cc825b12   ENGR00319415 pcie: random link down issue after warm-rst ... Browse Code »
    32

    There are about 0.02% percentage on some imx6q/dl/solo
    hw boards, random pcie link down when warm-reset is used.
    Make sure to clear the ref_ssp_en bit16 of gpr1 before
    warm-rst, and set ref_ssp_en after the pcie clks are
    stable to workaround it.

    rootcause:
    * gpr regisers wouldn't be reset by warm-rst, while the
    ref_ssp_en is required to be reset by pcie.
    (work-around in u-boot)
    * ref_ssp_en should be set after pcie clks are stable.
    (work-around in kernel)

    Signed-off-by: Richard Zhu

    Richard Zhu
     

18 Jun, 2014

1 commit

  • aae37d2a2   ENGR00319003 iMX6SX:HAB: Fixed build break when enabling secure boot ... Browse Code »

    When enabling "CONFIG_SECURE_BOOT", the build broken on iMX6SX platform
    due to two problems.

    1. The imximage tool in v2014 changes the command name of "SECURE_BOOT"
    to "CSF". Must update it in imximage.cfg scripts.

    2. The iMX6SX uses "CONFIG_ROM_UNIFIED_SECTIONS", but some HAB API
    definitions are not defined and cause compile errors.
    (HAB_RVT_REPORT_EVENT_NEW, HAB_RVT_REPORT_STATUS_NEW,
    HAB_RVT_AUTHENTICATE_IMAGE_NEW, HAB_RVT_ENTRY_NEW, HAB_RVT_EXIT_NEW)

    Signed-off-by: Ye.Li

    Ye.Li
     

17 Jun, 2014

5 commits