12 Nov, 2014
1 commit
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Add 14x14 arm2 nand support
Signed-off-by: Frank Li
23 Oct, 2014
1 commit
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supported NAND boot on 19x19 ARM2 board.
Signed-off-by: Allen Xu
09 Oct, 2014
1 commit
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Add android fastboot, recovery and booti support for mx6sx sabreauto board.
Signed-off-by: Ye.Li
26 Sep, 2014
2 commits
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Create mx6sx sabreauto BSP file and configurations. The devices below
have been supported:1. SD/MMC/eMMC on SDA/SDB (base board) sockets
2. USB OTG port and USB HOST port (base board)
3. NAND flash
4. QuadSPI flash on QSPI1
5. I2C
6. PMIC PFUZE100
7. Onboard ethernet chip on ENET2
8. Splash screen on LVDSSigned-off-by: Ye.Li
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Add support for i.MX6SX 14x14 lpddr2 arm2 board, same
as 17x17 arm2 except lpddr2 instead of ddr3.Signed-off-by: Nitin Garg
04 Sep, 2014
1 commit
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Couple of issues in commit 21a2eb5f. The RAM size is wrong and
max number of DCD is 220.Signed-off-by: Nitin Garg
29 Aug, 2014
1 commit
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Add support for i.MX6DQ/DL arm2 LPDDR2 boards.
Signed-off-by: Nitin Garg
25 Jun, 2014
1 commit
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The NOR flash PC28F00AG18 has 512 of 256KB erase blocks which are
locked after power on reset. Change the 17x17 ARM2 configurations
to match the flash parameters, and enable the CONFIG_SYS_FLASH_PROTECTION
to allow write to the flash.The EIM-NOR on 17x17 ARM2 board uses MUXed mode. This has less
effort on board rework.When boot from EIM-NOR, set SW8, SW7, SW5 to all off.
Signed-off-by: Ye.Li
17 Jun, 2014
21 commits
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The eMMC chip on iMX6SX SABRESD board is DNP at default. HW rework is
needed to weld it on the eMMC socket and disconnect SD card slot.The pins IOMUX of eMMC are different with SD card slot:
1. The eMMC uses 8 data pins, while SD card slot only uses 4 bits.
2. The CD pin used by SD card slot works as a data pin for eMMC.So adding a new u-boot target "mx6sxsabresd_emmc" for the eMMC support,
rather than using the SD boot configuration.Signed-off-by: Ye.Li
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Add BSP codes to mx6sxsabresd to support android uboot features:
fastboot, booti and recoverySigned-off-by: Ye.Li
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T support M4 boot in 50 ms, kick start M4 at "board_early_init_f"
stage where u-boot passes ARM and architecture initialization.Add a configuration "CONFIG_SYS_AUXCORE_FASTUP" for this feature
enablement. And a build config "mx6sxsabresd_m4fastup".
Adjust the default M4 image address to 0x78000000 represented by
"CONFIG_SYS_AUXCORE_BOOTDATA".When M4 fast boot is enabled, RDC should be enabled together and
the QSPI driver must turn off, because M4 is running on QSPI flash
in XIP. Setup this relationship by configurations.Signed-off-by: Ye.Li
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Add BSP codes for iMX6SX SABRE SD board to support SD/MMC,
USB, QSPI2 NOR Flash, Ethernet, I2C, PMIC and
M4 command boot(bootaux).Add board build targets of SABER SD for boot device:
mx6sxsabresd --- SD/MMC
mx6sxsabresd_qspi2 --- QuadSPI2 NOR flashSigned-off-by: Ye.Li
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Add script "imximage_lpddr2.cfg" for DDR controller settings of LPDDR2.
Modify "plugin.S" for LPDDR2.
Add build target for 19x19 LPDDR2 ARM2 board.Signed-off-by: Ye.Li
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Add BSP codes for iMX6SX 19x19 DDR3 ARM2 board to support SD/MMC,
USB, QSPI2 NOR Flash, SPI NOR flash, WEIM NOR Flash, Ethernet,
I2C, PMIC and M4 command boot(bootaux).Some features has conflicts, so can't be enabled at same time:
WEIM-NOR QSPI pin conflict
QSPI SPI-NOR u-boot driver conflict
SPI-NOR SD2 pin conflictAdd board build targets of 19x19 DDR3 ARM2 for boot device:
mx6sx_19x19_ddr3_arm2 --- SD/MMC/eMMC
mx6sx_19x19_ddr3_arm2_spinor --- SPINOR on ECSPI4 CS0
mx6sx_19x19_ddr3_arm2_eimnor --- WEIM NOR flash
mx6sx_19x19_ddr3_arm2_qspi2 --- QuadSPI2 NOR flashSigned-off-by: Ye.Li
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Add BSP codes for iMX6SX 17x17 ARM2 board to support SD/MMC,
USB, QSPI2 NOR Flash, SPI NOR flash, NAND Flash, Ethernet, I2C
,PMIC and M4 command boot (bootaux).Some features has conflicts, so can't be enabled at same time:
QSPI NAND pin conflict
QSPI SPI-NOR u-boot driver conflict
SPI-NOR SD2 pin conflictAdd board build targets of 17x17 ARM2 for boot device:
mx6sx_17x17_arm2 --- SD/MMC/eMMC
mx6sx_17x17_arm2_spinor --- SPINOR on ECSPI4 CS0
mx6sx_17x17_arm2_nand --- NAND flash
mx6sx_17x17_arm2_qspi2 --- QuadSPI2 NOR flashSigned-off-by: Ye.Li
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Default imx6slevk BSP supports SPI NOR flash read, write and erase by using
"sf" command.
The "mx6slevk_spinor" builds the uboot that can be booted from SPI NOR flash
and stored the environments variables in it.Signed-off-by: Ye.Li
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Sabreauto board has pin conflict (pin EIM_D18) between NOR flash
and i2c3. To enable the USB host, the i2c3 must be used to operate
the max7310 IO expander to output the VBUS power.As SPINOR is enabled at default, it is impossible to use USB host
at same time. Thus, remove the SYS_USE_SPINOR from sabreauto
configurations to disable SPINOR.Signed-off-by: Ye.Li
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Add build targets for enabling android support on i.mx6sabreauto/sabresd and
i.mx6slevk boardsSigned-off-by: Ye.Li
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This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2
shared the same board with i.MX6Q ARM2 board since the i.MX6DL is
pin-pin compatible with i.MX6Q.The patch also support the DDR 32-BIT mode option. Please define
CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT
mode.But due to the board design, it's 64bit DDR buswidth physically,
so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it.The patch has been tested on the i.MX6Q and i.MX6DL arm2 board.
Signed-off-by: Jason Liu
Signed-off-by: Ye.Li -
This patch add the plugin mode support for sabreauto board.
In order to enable the plugin mode, please turn on the
CONFIG_USE_PLUGIN in the include/configs/mx6qsabre_common.hSigned-off-by: Jason Liu
Signed-off-by: Ye.Li -
This patch adds the SATA support for i.mx6qsabresd and
i.mx6qsabreauto boardSigned-off-by: Jason Liu
Signed-off-by: Ye.Li -
Add the GPMI nand support to the iMX6 sabreauto:
--Enable the GPMI NAND at default.
--Enable the clocks
--Set the default environment for nand bootSigned-off-by: Huang Shijie
Signed-off-by: Jason Liu
Signed-off-by: Ye.Li -
Add the WEIM-NOR support
Signed-off-by: Jason Liu
Signed-off-by: Ye.Li -
This patch adds the SPI-NOR support for the i.mx6q/dl/solo:sabresd/auto board:
- Support the SPI-NOR function with sf command,
- Support the enviroment from SPI-NOR when CONFIG_SYS_BOOT_SPINORSigned-off-by: Jason Liu
Signed-off-by: Ye.Li -
This patch is to add the i.MX6solo sabreauto support,
The i.MX6solo sabreauto board configuration has the following
difference with i.MX6dl sabreauto:- DDR bus width: 32bit
- DDR capacity: 1024MSigned-off-by: Jason Liu
Signed-off-by: Ye.Li -
This patch is to add the i.MX6DL sabreauto board support.
i.MX6DL sabreauto board share the same design with i.MX6Q
sabreauto board except the SOC difference.The DDR script has been updated to the v0.2 version from
ddr-scripts-rel.git, the commit based on is:
bfd157a Updated MX6DL and MX6DQ ARD and SabreSD scriptsSigned-off-by: Jason Liu
Signed-off-by: Ye.Li -
Rename the imximage.cfg to mx6q.cfg.
No function change at all.Signed-off-by: Ye.Li
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The i.MX6solo sabre-sd board configuration has the following
difference with i.MX6dl sabre-sd:- DDR bus width: 32bit
- DDR capacity: 512MSigned-off-by: Ye.Li
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1. Make the DDR size configurable based on the boards.cfg
2. Make the FDT file configurable based on the boards.cfg
3. Add DDR and boot configuration script for iMX6dl.
Change default boot from SD card.
The DDR script has been updated to the v1.5 version from ddr-scripts-rel
commit: bfd157a Updated MX6DL and MX6DQ ARD and SabreSD scripts.Signed-off-by: Ye.Li
13 Jun, 2014
1 commit
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Add BSP codes to support SPI NOR flash read, write and erase by using
"sf" command.
In addition, add a new configuration "mx6slevk_spinor" for building
the uboot that can be booted from SPI NOR flash and stored the
environments variables in it.Signed-off-by: Ye.Li
Signed-off-by: Nitin Garg
25 Mar, 2014
1 commit
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Trivial merge conflict, needed to manually remove
local_info as per commit 41364f0f.Conflicts:
board/samsung/common/board.c
14 Mar, 2014
1 commit
12 Mar, 2014
1 commit
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Gateworks Ventana is a product family based on the i.MX6. This
patch adds support for all boards in the Ventana family. Where
possible, data from the boards EEPROM is used to determine various
details about the board at runtime.Signed-off-by: Tim Harvey
11 Mar, 2014
3 commits
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Some recent changes got parts of the file out of order again, correct.
Signed-off-by: Tom Rini
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When I cc board maintainers, some of them result in
bounce mails.It turned out the following do not work any more:
Yuli Barcohen
Travis Sawyer
Yusdi Santoso
David Updegraff
Sangmoon Kim
Anton Vorontsov
Blackfin Team
Bluetechnix Tinyboards
Andre SchwarzFor the blackfin boards where Sonic Zhang is also listed
as a maintainer, dead addresses should be simply dropped.For all of the others, the status should be changed to "Orphan".
We have adopted the definition of "Orphan" as:
board is not actively maintained any more but still builds, and any
address associated with it is that of the last known maintainer(s)Even though the emails do not work any more, they carry information.
We want to keep them.Besides, Orphan boards have been collected at the bottom of boards.cfg.
(This is done when we run "tools/reformat.py")Add separators to distinguish them from those which
were moved to Orphan 6 months ago.
I believe it will be helpful in future to find which boards are
old enough to be removed from the code base.Signed-off-by: Masahiro Yamada
Cc: Detlev Zundel
Cc: Tom Rini
Cc: Albert ARIBAUD
10 Mar, 2014
2 commits
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CONFIG_SYS_HZ must be always 1000, but M5271EVB.h defines it
as 1000000 and idmr.h defines it as (50000000 / 64).When compiling these two boards, a warning message is displayed:
time.c:14:2: warning: #warning "CONFIG_SYS_HZ must be 1000
and should not be defined by platforms" [-Wcpp]There are no board maintainers for them so this commit just
deletes them.Signed-off-by: Masahiro Yamada
Cc: Jason Jin -
Add sama5d3 Xplained board support which use Atmel SAMA5D36 SoC.
Now it supports boot from NAND flash and SD/MMC card.
Features support:
- NAND flash
- SD/MMC card
- Two USB hosts
- Ethernet (one GMAC, one EMAC)Signed-off-by: Bo Shen
[reorder boards.cfg]
Signed-off-by: Andreas Bießmann
08 Mar, 2014
2 commits
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T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
It works in two mode: standalone mode and PCIe endpoint mode.T2080PCIe-RDB Feature Overview
------------------------------
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
DDR Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LP devices
- 72bit 4GB DDR3-LP SODIMM in slot
Ethernet interfaces:
- Two 10M/100M/1G RGMII ports on-board
- Two 10Gbps SFP+ ports on-board
- Two 10Gbps Base-T ports on-board
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes 16 lanes configuration:
- SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
- SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
- SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
- SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
- SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
- SerDes-2 Lane G-H: to SATA1 & SATA2
IFC/Local Bus:
- NOR: 128MB 16-bit NOR flash
- NAND: 512MB 8-bit NAND flash
- CPLD: for system controlling with programable header on-board
eSPI:
- 64MB N25Q512 SPI flash
USB:
- Two USB2.0 ports with internal PHY (both Type-A)
PCIe:
- One PCIe x4 gold-finger
- One PCIe x4 connector
- One PCIe x2 end-point device (C293 Crypto co-processor)
SATA:
- Two SATA 2.0 ports on-board
SDHC:
- support a TF-card on-board
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial portsSigned-off-by: Shengzhou Liu
Reviewed-by: York Sun
