19 Jun, 2014
4 commits
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nios-32 arch was removed back in 2010 (1117cbf). Code depending on
its headers (nios.h, nios-io.h) can't possibly compile since then.
As it wasn't fixed till now it is safe to remove.Signed-off-by: Vasili Galka
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commit 18b06652cd "tools: include u-boot version of sha256.h"
unconditionally forced the sha256.h from u-boot to be used
for tools instead of the host version. This is fragile though
as it will also include the host version. Therefore move it
to include/u-boot to join u-boot/md5.h etc which were renamed
for the same reason.cc: Simon Glass
Signed-off-by: Jeroen Hofstee -
Fix the following warning messages:
In function 'flash_erase': 180:21:
warning: variable 'last' set but not used [-Wunused-but-set-variable]
In function 'write_buff': 322:10:
warning: variable 'port_width' set but not used [-Wunused-but-set-variable]Signed-off-by: Masahiro Yamada
Cc: TsiChung Liew -
From comparison of current logic and the logic that was prior to commit
aba27ac, we see that first parameter of FPGA_GET_REG() shall be the
FPGA index and not channel number. The re-factoring in commit aba27ac
accidentally changed that.Cc: Stefan Roese
Acked-by: Dirk Eibach
Signed-off-by: Vasili Galka
12 Jun, 2014
10 commits
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Clang interpretes an if condition like "if ((a = b) == NULL)
as it tries to assign a value in a statement. Hence if you do
"if ((something)) it warns you that you might be confused.
Hence drop the double braces for plane if statements.cc: Holger Brunck
Signed-off-by: Jeroen Hofstee -
cc: Troy Kisky
Signed-off-by: Jeroen Hofstee -
this prevent some warnings when compiling with clang
cc: Stelian Pop
Signed-off-by: Jeroen Hofstee -
Signed-off-by: Vasili Galka
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This prevents some warnings when building with clang.
cc:: andreas.devel@googlemail.com
Signed-off-by: Jeroen Hofstee -
Most of the warnings seem to be related to using 'int' for size_t. Change
this and fix up the remaining warnings and problems. For bootm, the warning
was masked by others, and there is an actual bug in the code.Signed-off-by: Simon Glass
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run_command() returns 0 for success, 1 for failure. Fix places which
assume that failure is indicated by a negative return code.Signed-off-by: Thomas Betker
Acked-by: Simon Glass
Tested-by: Simon Glass
Tested-by: Stefan Roese -
Correct the binary output so that image_binary_size is really at the
end of the image.Signed-off-by: Simon Glass
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Correct the binary output so that image_binary_size is really at the
end of the image.Signed-off-by: Simon Glass
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This should include the hash so that image_binary_size is really at the
end of the image, and not some 300 bytes earlier.Signed-off-by: Simon Glass
08 Jun, 2014
1 commit
07 Jun, 2014
7 commits
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This family is supported by the TPS65218 PMIC. Implement a scale_vcores
to set the MPU and CORE voltage correctly to the max frequency that is
supported (and what we will be scaling them to in setup_dplls()).Signed-off-by: Tom Rini
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Signed-off-by: Tom Rini
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Cc: trini@ti.com
Signed-off-by: Hannes Petermaier -
if we have no NAND-Chip, we don't need the gpmc-controller and therefore
is no need to init it.Cc: trini@ti.com
Signed-off-by: Hannes Petermaier -
Cc: trini@ti.com
Signed-off-by: Hannes Petermaier -
The ePOS EVM and EVM SK have QSPI as an option to boot. Add a qspiboot
target that utilizes QSPI for env and so forth as an example of best
practices. As QSPI is booted from directly we need to chang
CONFIG_SYS_TEXT_BASE.Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices
we need to handle that elsewhere, once NAND support is also added.Signed-off-by: Sourav Poddar
Signed-off-by: Tom Rini -
OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros
to configure GPMC controller for x7 or x8 bit device connected to its interface.
Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above
macros can be completely removed.Signed-off-by: Pekon Gupta
06 Jun, 2014
9 commits
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Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.Also update README.scrapyard.
Signed-off-by: Masahiro Yamada
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Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.Signed-off-by: Masahiro Yamada
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Because cmd_mkimage is used in various subdirectories,
it seems reasonable to define it in scripts/Makefile.lib.Signed-off-by: Masahiro Yamada
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Crossbars and IDT were not getting configured for Serdes2 protocol
0x9d for B4420.Signed-off-by: Poonam Aggrwal
Signed-off-by: Shaveta Leekha
Reviewed-by: York Sun -
A-007186: SerDes PLL is calibrated at reset. It is possible
for jitter to increase and cause the PLL to unlock when the
temperature delta from the time the PLL is calibrated exceeds
+56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using
XnVDD of 1.5 V). No issues are seen with LC VCO. The protocols
only using Ring VCOs are impacted.Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring
VCO, this need to use alternate serdes protocols. Alternate
option has the same functionality as the original option; the
only difference being LC VCO rather than Ring VCO.Signed-off-by: Chunhe Lan
Reviewed-by: York Sun -
- add support for 2nd DIMM slot.
- make it work with DIMM which is less than 2GB.Verified with two 2GB UDIMM MT9JSF25672AZ-2G1K1 in two DIMM slots.
Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to
increase and cause the PLL to unlock when the temperature delta from the
time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V
(or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC
VCO. Only the protocols using Ring VCOs are impacted.Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need
to use alternate serdes protocols. The alternate option has the same
functionality as the original option; the only difference being LC VCO
rather than Ring VCO.Signed-off-by: Shaohui Xie
Reviewed-by: York Sun -
As errata A-007186, we need to use the alternate serdes
protocol instead of those impacted protocols.- add support for serdes protocols: 0x1b, 0x50, 0x5e,
0x64, 0x6a, 0xd2, 0x67, 0x70.
- update t2080_rcw.cfg to adapt to new rcw_66_15 for
t2080qds and t2080rdb.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun
02 Jun, 2014
1 commit
31 May, 2014
8 commits
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This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denx -
This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denx -
This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denx -
This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denx -
This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denx -
This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denx -
This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denx -
This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denx