Eric Lee / smarc-uboot

07 May, 2018

1 commit

  • 83d290c56   SPDX: Convert all of our single license tags to Linux Kernel style ... Browse Code »
    56

    When U-Boot started using SPDX tags we were among the early adopters and
    there weren't a lot of other examples to borrow from. So we picked the
    area of the file that usually had a full license text and replaced it
    with an appropriate SPDX-License-Identifier: entry. Since then, the
    Linux Kernel has adopted SPDX tags and they place it as the very first
    line in a file (except where shebangs are used, then it's second line)
    and with slightly different comment styles than us.

    In part due to community overlap, in part due to better tag visibility
    and in part for other minor reasons, switch over to that style.

    This commit changes all instances where we have a single declared
    license in the tag as both the before and after are identical in tag
    contents. There's also a few places where I found we did not have a tag
    and have introduced one.

    Signed-off-by: Tom Rini

    Tom Rini
     

31 Jan, 2018

2 commits

  • c0c32af0b   drivers/ddr/fsl: Add 3DS RDIMM support ... Browse Code »

    On top of RDIMM support, add new register calculation to support
    3DS RDIMMs. Only symmetrical 3DS is supported at this time.

    Signed-off-by: York Sun

    York Sun
     
  • 426230a65   drivers/ddr/fsl: Fix DDR4 RDIMM support ... Browse Code »

    For DDR4, command/address delay in mode registers and parity latency
    in timing config register are only needed for UDIMMs, but not RDIMMs.
    Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for
    dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix
    calculation of timing config registers. Use hexadecimal format for
    printing RCW (register control word) registers.

    Signed-off-by: York Sun

    York Sun
     

13 Apr, 2017

1 commit

19 Jan, 2017

1 commit

  • 031acdbae   armv8/fsl_lsch2: Add chip power supply voltage setup ... Browse Code »

    Set up chip power supply voltage according to voltage ID.
    The fuse status register provides the values from on-chip
    voltage ID fuses programmed at the factory. These values
    define the voltage requirements for the chip.

    Main operations:
    1. Set up the core voltage
    2. Set up the SERDES voltage and reset SERDES lanes
    3. Enable/disable DDR controller support 0.9V if needed

    Signed-off-by: Hou Zhiqiang
    Reviewed-by: York Sun

    Hou Zhiqiang
     

06 Dec, 2016

1 commit

  • 02fb27615   fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum ... Browse Code »

    - add additional function erratum_a009942_check_cpo to check if the
    board needs tuning CPO calibration for optimal setting.
    - move ERRATUM_A009942(with revision to check cpo_sample option) from
    fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
    - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
    - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.

    Signed-off-by: Shengzhou Liu
    [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
    Reviewed-by: York Sun

    Shengzhou Liu
     

15 Sep, 2016

1 commit

18 May, 2016

3 commits

22 Mar, 2016

1 commit

26 Jan, 2016

1 commit

  • a994b3deb   driver/ddr/fsl: Add workaround for A009663 ... Browse Code »

    Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
    before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
    to the desired value after DDR initialization has completed.

    When DDR controller is configured to operate in auto-precharge
    mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.

    Signed-off-by: Shengzhou Liu
    Reviewed-by: York Sun

    Shengzhou Liu
     

19 Jan, 2016

1 commit

  • 5b8031ccb   Add more SPDX-License-Identifier tags ... Browse Code »
    40

    In a number of places we had wordings of the GPL (or LGPL in a few
    cases) license text that were split in such a way that it wasn't caught
    previously. Convert all of these to the correct SPDX-License-Identifier
    tag.

    Signed-off-by: Tom Rini

    Tom Rini
     

14 Dec, 2015

1 commit

31 Oct, 2015

1 commit

23 Apr, 2015

2 commits

12 Dec, 2014

1 commit

  • a7787b785   fsl/sleep: updated the deep sleep framework for QorIQ platforms ... Browse Code »

    With the introducing of generic board and ARM-based cores, current
    deep sleep framework doesn't work anymore.
    This patch will convert the current framework to adapt this change.
    Basically it does:
    1. Converts all the Freescale's DDR driver to support deep sleep.
    2. Added basic framework support for ARM-based and PPC-based
    cores separately.

    Signed-off-by: Tang Yuantian
    Reviewed-by: York Sun

    Tang Yuantian
     

25 Sep, 2014

2 commits

  • bb5783224   driver/ddr/fsl: Fix tXP and tCKE ... Browse Code »

    The driver was written using old DDR3 spec which only covers low speeds.
    The value would be suboptimal for higher speeds. Fix both timing according
    to latest DDR3 spec, remove tCKE as an config option.

    Signed-off-by: York Sun

    York Sun
     
  • 1d71efbb0   driver/ddr: Restruct driver to allow standalone memory space ... Browse Code »

    U-boot has been initializing DDR for the main memory. The presumption
    is the memory stays as a big continuous block, either linear or
    interleaved. This change is to support putting some DDR controllers
    to separated space without counting into main memory. The standalone
    memory controller could use different number of DIMM slots.

    Signed-off-by: York Sun

    York Sun
     

09 Sep, 2014

1 commit

  • ef87cab66   driver/ddr/fsl: Add support of overriding chip select write leveling ... Browse Code »

    JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
    is not an issue unless some DQ pins are not connected. If a platform uses
    regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
    those floating pins for the second rank. The workaround is to use a known
    good chip select for this purpose.

    Signed-off-by: York Sun

    York Sun
     

23 Apr, 2014

2 commits

22 Feb, 2014

1 commit

26 Nov, 2013

1 commit