Eric Lee / smarc-uboot

23 Oct, 2014

1 commit

22 Oct, 2014

1 commit

20 Oct, 2014

3 commits

11 Oct, 2014

1 commit

09 Oct, 2014

4 commits

08 Oct, 2014

1 commit

30 Sep, 2014

1 commit

29 Sep, 2014

1 commit

26 Sep, 2014

2 commits

25 Sep, 2014

1 commit

  • 2115fc7d4   sf: probe: Fix quad bit set path ... Browse Code »

    Currently, flash quad bit is set in "spi_flash_validate_params" and later
    at the end in the same api, we write 0 to status register for few flashes,
    thereby overriding the quad bit set. This fix moves the quad bit setting
    outside this api in "spi_flash_probe_slave"

    Signed-off-by: Sourav Poddar
    Reviewed-by: Jagannadha Sutradharudu Teki

    Poddar, Sourav
     

23 Sep, 2014

1 commit

18 Sep, 2014

6 commits

11 Sep, 2014

1 commit

10 Sep, 2014

1 commit

05 Sep, 2014

2 commits

  • aa76a7e47   ENGR00329484-2 ARM:MX6: Clear Align bit in SCTLR ... Browse Code »
    5

    This problem is found when debugging QuadSPI. When "A" bit is enabled,
    unaligned access will cause data abort exception. Actually, we do not
    want this exception. So clear the align bit for MX6 SOCs.

    Tested this code with android team colleague and did not find problem.

    Signed-off-by: Peng Fan

    Peng Fan
     
  • 0338ad3a3   ENGR00329484-1 QuadSPI:Unaligned access crash uboot ... Browse Code »

    To fsl_qspi_write_data and fsl_qspi_ip_read, pointer txbuf and
    rxbuf are not guaranteed that they are 4 Bytes aligned. Also,
    it it not a good idea to cast type 'u8 *' to 'u32 *', except
    we are sure that pointer type 'u8 *' is 4 Bytes aligned and
    cast it to 'u32 *' will not pass memory boundary.

    The problem is found when using fsl_qspi_write_data to write
    registers in flash devices. The err msg:

    data abort
    pc : [] lr : []
    sp : bf5512c8 ip : 0000001c fp : bf856608
    r10: 87868904 r9 : bf551efc r8 : 200f048c
    r7 : 00000002 r6 : bf551336 r5 : bf552a70 r4 : 00000001
    r3 : 00000000 r2 : 00000060 r1 : 8783b520 r0 : 8783b520
    Flags: nZCv IRQs on FIQs off Mode SVC_32
    Resetting CPU ...

    The asm code which cause data abort is:
    87822f30: e5964000 ldr r4, [r6]
    From the dump msg, r6 is not 4 Bytes aligned, and data abort exception.

    So, Use mempcy but not unsafe type casting.

    In this patch, max_write_size is assigned using txfifo to avoid possible
    errors in future.

    Signed-off-by: Peng Fan

    Peng Fan
     

04 Sep, 2014

1 commit

02 Sep, 2014

1 commit

30 Aug, 2014

1 commit

  • ac6272627   ENGR00323255 Fixed QSPI randomly access timeout issue ... Browse Code »

    The QSPI clock rate was set without disabling the clock gate, the
    randomly glitch may mess up the clock and there will be no clock output,
    when kernel boot up the QSPI access will fail.

    To debug this issueon i.MX6SX SDB, changed the u-boot bootscript to 'sf probe; reset'
    to keep rebooting, the issue can be reproduced in 20 mins, set clock out
    register in CCM and measured TP86, found there is no clock ouput.

    To fix this bug, disable clock gate before changing clock rate.
    NOTICE: QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, need
    to disable both of them.

    Signed-off-by: Allen Xu

    Allen Xu
     

29 Aug, 2014

1 commit

26 Aug, 2014

2 commits

25 Aug, 2014

1 commit

  • 53118db42   ENGR00328312 i2c: imx: Optimize the i2c device recovery solution ... Browse Code »
    12

    From i2c spec, if device pull down the SDA line that causes
    i2c bus dead, host can send out 9 clock to let device release
    SDA.

    But for some special device like pfuze100, it pull down SDA line
    and the solution cannot take effort.

    The patch just add NACK and STOP signal after 8 dummy clock, and pmic
    can release SDA line after the recovery. Test case catch 375 times of
    i2c hang, and all are recovered.

    Signed-off-by: Fugang Duan

    Fugang Duan
     

15 Aug, 2014

1 commit

  • 01996acd7   ENGR00326994 iMX6: Checking PLL2 PFD0 and PFD2 for periph_clk before reset ... Browse Code »

    u-boot v2014 upstream codes have a problem in pfd reset (s_init function)
    that imx6 Dual is not applied for PLL2 PFD2 reset. It is originated by
    using dynamical cpu type checking and introducing two cpu types:
    MXC_CPU_MX6Q and MXC_CPU_MX6D for iMX6 Dual/Quad platform.

    Fixed this problem by checking the pre_periph_clk_sel and pre_periph2_clk
    of CCM CBCMR register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock
    source, do not reset this PFD to avoid system hang.

    Signed-off-by: Ye.Li

    Ye.Li
     

08 Aug, 2014

1 commit

07 Aug, 2014

2 commits

04 Aug, 2014

1 commit

  • 45fa2ad38   ENGR00325088 video: mxsfb: Disable LCDIF correctly ... Browse Code »
    5

    Let's use the i.MX common miscellaneous reset API
    to reset the LCDIF block so that we may eliminate
    a random hang issue at the arch_preboot_os() stage
    when we disable the LCDIF. This patch also waits
    for a VSYNC interrupt to guarantee the reset is
    done at the VSYNC edge, which somehow makes the
    LCDIF consume the display FIFO(?) and helps the
    LCDIF work normally at the kernel stage.

    Tested-by: Jason Liu
    Tested-by: Sandor Yu
    Tested-by: Ye.Li
    Tested-by: Guo Sally
    Signed-off-by: Liu Ying

    Liu Ying
     

31 Jul, 2014

1 commit

  • ec78595a2   ENGR00325255 pcie:enable pcie support on imx6sx sd ... Browse Code »
    32

    Enable pcie support in uboot on imx6sx sd boards
    - enable_pcie_clock should be call before ssp_en is set,
    since that ssp_en control the phy_ref clk gate, turn on
    it after the source of the pcie clks are stable.
    - add debug info
    - add rx_eq of gpr12 on imx6sx
    - there are random link down issue on imx6sx. It's
    pcie ep reset issue.
    solution:reset ep, then retry link can fix it.

    Signed-off-by: Richard Zhu

    Richard Zhu