31 Jan, 2018
2 commits
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On top of RDIMM support, add new register calculation to support
3DS RDIMMs. Only symmetrical 3DS is supported at this time.Signed-off-by: York Sun
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For DDR4, command/address delay in mode registers and parity latency
in timing config register are only needed for UDIMMs, but not RDIMMs.
Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for
dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix
calculation of timing config registers. Use hexadecimal format for
printing RCW (register control word) registers.Signed-off-by: York Sun
13 Apr, 2017
1 commit
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This function name shadows a global name but is in fact different. This
is very confusing. Rename it to help with the following refactoring.Signed-off-by: Simon Glass
19 Jan, 2017
1 commit
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Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if neededSigned-off-by: Hou Zhiqiang
Reviewed-by: York Sun
06 Dec, 2016
1 commit
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- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.Signed-off-by: Shengzhou Liu
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun
15 Sep, 2016
1 commit
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32 more debug registers are added for newer DDR controllers.
Signed-off-by: York Sun
Signed-off-by: Shengzhou Liu
18 May, 2016
3 commits
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The initial training for the DDRC may provide results that are not
optimized. The workaround provides better read timing margins.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
Per the latest erratum document, update step 4 and step 8, only
DEBUG_29[21] is changed, all other bits should not be changed.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun
22 Mar, 2016
1 commit
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Add support of address parity for DDR4 UDIMM or discrete memory.
It requires to configurate corresponding MR5[2:0] and
TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig,
e.g. hwconfig=fsl_ddr:parity=on.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun
26 Jan, 2016
1 commit
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Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.When DDR controller is configured to operate in auto-precharge
mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun
19 Jan, 2016
1 commit
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In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert all of these to the correct SPDX-License-Identifier
tag.Signed-off-by: Tom Rini
14 Dec, 2015
1 commit
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DDR4 has different RTT value and code according to JEDEC spec. Update
the macros and options .Signed-off-by: York Sun
31 Oct, 2015
1 commit
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SR_IE(Self-refresh interrupt enable) is needed for
Hardware Based Self-Refresh. Make it configurable and let
board code handle the rest.Signed-off-by: Joakim Tjernlund
Reviewed-by: York Sun
23 Apr, 2015
2 commits
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The LS2085AQDS is an evaluatoin platform that supports the LS2085A
family SoCs. This patch add basic support of the platform.Signed-off-by: York Sun
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Bhupesh Sharma -
This erratum only applies to general purpose DDR controllers in LS2.
It shouldn't be applied to DP-DDR controller. Check DDRC versoin number
before applying workaround.Signed-off-by: York Sun
12 Dec, 2014
1 commit
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With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun
25 Sep, 2014
2 commits
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The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 spec, remove tCKE as an config option.Signed-off-by: York Sun
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U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.Signed-off-by: York Sun
09 Sep, 2014
1 commit
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JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.Signed-off-by: York Sun
23 Apr, 2014
2 commits
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When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun -
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.Signed-off-by: York Sun
22 Feb, 2014
1 commit
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Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.Signed-off-by: York Sun
26 Nov, 2013
1 commit
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Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.Signed-off-by: York Sun