15 Jul, 2015
40 commits
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Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
ensuring that the host bridge is configured.Reviewed-by: Bin Meng
Signed-off-by: Simon Glass -
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
The layout of the ROM is a bit hard to discover by reading the code. Add
a table to make it easier.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Enable a SPI environment and store it in a suitable place.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Jagan Teki -
The logic is incorrect and currently has no effect. Fix it so that we can
write to SPI flash, since by default it is write-protected.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Tested-by: Andrew Bradford -
The status register on ICH9 is a single byte, so use byte access when
writing to it, to avoid updating the control register also.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Jagan Teki -
Store VESA parameters to Linux setup header so that vesafb driver
in the kernel could work.Signed-off-by: Bin Meng
Acked-by: Simon Glass
Tested-by: Jian Luo -
Enable graphics support on Intel Crown Bay board With the help of
vgabios for Intel TunnelCreek IGD. Tested with an external LVDS
panel connected to X4 connector and SDVO adapter connected to X9
connector on the board.Signed-off-by: Jian Luo
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code,
hence remove it.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Print the meaningful base address and mask of an MTRR range without showing
the memory type encoding or valid bit.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Per CPUID:80000008h result, the maximum physical address bits of
TunnelCreek processor is 32 instead of default 36. This will fix
the incorrect decoding of MTRR range mask.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
We should setup fixed range MTRRs for some legacy regions like VGA
RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
other cache settings, but we can override this in x86_cpu_init_f().Signed-off-by: Bin Meng
Acked-by: Simon Glass -
The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit
color depth is configured. Since 24-bit mode already uses 4 bytes
internally, it should be OK to just add this option in switch case.Signed-off-by: Jian Luo
Acked-by: Simon Glass
Tested-by: Bin Meng -
We should allow pci config read/write to host bridge (b.d.f = 0.0.0)
in the int1a_handler() which is a valid pci device.Signed-off-by: Jian Luo
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
PCI option rom may use different SS during its execution, so it is not
safe to assume esp pointed to the same location in the protected mode.Signed-off-by: Jian Luo
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Per PCI spec, VGA device reports its class as standard 030000h in
its configuration space, so we can use it to determine if we need
run option rom instead of testing the supported vendor/device ids.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it
so that sub-buses are numbered correctly.Signed-off-by: Simon Glass
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Only the PCI controller has access to the PCI region information. Make sure
to use the controller (rather than any attached bridges) when configuring
devices.This corrects a failure to scan and configure devices when driver model is
enabled for PCI.Also add a comment to explain the problem.
Signed-off-by: Simon Glass
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So far interrupt routing works pretty well for any on-chip devices
on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
Linux kernel is smart enough to do interrupt swizzling and figure
out device's irq using its parent bridge's interrupt routing info
all the way up to its root port. In U-Boot all PCIe root ports'
interrupts were routed to PIRQ E/F/G/H before, while actually all
PCIe downstream ports received INTx are routed to PIRQ A/B/C/D
directly and not configurable. Now we change this mapping so that
any external PCIe device can work correctly.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Enable writing MP table for Intel Crown Bay board.
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Document U-Boot multi-processor support as well as configuration
tables like SFI and MP tables for SMP OS kernel.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Implement write_mp_table() to create a minimal working MP table.
This includes an MP floating table, a configuration table header
and all of the 5 base configuration table entries. The I/O interrupt
assignment table entry is created based on the same information used
in the creation of PIRQ routing table from device tree. A check
duplicated entry logic is applied to prevent writing multiple I/O
interrupt entries with the same information.Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we
need actually write the MP table at the F seg, just like we did for
PIRQ routing and SFI tables. With MP table existence, linux kernel
will switch to I/O APIC and local APIC to process all the peripheral
interrupts instead of 8259 PICs. This takes full advantage of the
multicore hardware and the SMP kernel.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
The MP table provides a way for the operating system to support
for symmetric multiprocessing as well as symmetric I/O interrupt
handling with the local APIC and I/O APIC. We provide a bunch of
APIs for U-Boot to write the floating table, configuration table
header as well as base and extended table entries.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Remove inline for lapic access routines and expose lapic_read()
& lapic_write() as APIs to read/write lapic registers. Also move
stop_this_cpu() to mp_init.c as it has nothing to do with lapic.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
I/O APIC registers are addressed indirectly. Add io_apic_read() and
io_apic_write() routines to help register access. Two macros for I/O
APIC ID and version register offset are also added.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Remove all the dead/unused macros from asm/ioapic.h.
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
There is no need to populate multiple irq info entries with the same
bus number and device number, but with different interrupt pin. We
can use the same entry to store all the 4 interrupt pin (INT A/B/C/D)
routing information to reduce the whole PIRQ routing table size.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
In fill_irq_info() pci device's function number is written into
the table, however this is not really necessary. The function
number can be anything as OS doesn't care about this field,
neither does the PIRQ routing specification. Change to always
writing 0 as the function number.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
We should write correct bus number to the PIRQ routing table for the
irq router from device tree, instead of hard-coded zero.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
There are 4 usb ports on the Intel Crown Bay board, 2 of which are
connected to Topcliff usb host 0 and the other 2 connected to usb
host 1. USB devices inserted in the ports connected to usb host 1
cannot get detected due to wrong IRQ assigned to the controller.
Actually we need apply the PCI interrupt pin swizzling logic to all
devices on the Topcliff chipset when configuring the PIRQ routing.This was observed on usb ports, but device 6 and 10 irqs are also
wrong. Correct them all together.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Add a RTC node in the device tree to enable DM RTC support.
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Currently CONFIG_DM_I2C is used in cmd_date.c for driver model,
but it should be actually CONFIG_DM_RTC.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Add driver model support to the mc146818 rtc driver. Also clean up
the driver a little bit for coding convention issues.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Intel Crown Bay board has a TunnelCreek processor which supports
hyper-threading. Add /cpus node in the crownbay.dts and enable
the MP initialization.Signed-off-by: Bin Meng
Acked-by: Simon Glass
Signed-off-by: Simon Glass
(modified to remove error:
overriding the value of OF_CONTROL. Old value: "y", new value: "y") -
This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit
defines into arch/x86/include/asm/lapic.h
- Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
- Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and
CONFIG_AP_IN_SIPI_WAIT
- Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as
it is not apic related and only used by ivybridge
- Fix coding convention issuesSigned-off-by: Bin Meng
Acked-by: Simon Glass -
Currently lapic_setup() is called before calling mp_init(), which
then calls init_bsp() where it calls enable_lapic(), which was
already enabled in lapic_setup(). Hence move lapic_setup() call
into init_bsp() to avoid the duplication.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the
new 'get_count' method for baytrail and cpu_x86 drivers. Now we call
cpu_get_count() in mp_init() to get the number of CPUs.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Ivybridge is not ready for U-Boot MP initialization yet.
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Introduce a new method 'get_count' in the UCLASS_CPU ops to get
the number of CPUs in the system.Signed-off-by: Bin Meng
Acked-by: Simon Glass
