21 Nov, 2014
1 commit
-
Current uboot does not support bmode sd3. So add this to make
'bmode sd3' command in uboot can work fine.Signed-off-by: Peng Fan
(cherry picked from commit 8f9c61e391687f9ef6e1f735040bd0d679320215)
16 Nov, 2014
2 commits
-
Modified the mtd index for imx6 sabreauto board, split the parallel nor
to two partitions and the NAND index could be align with imx6sx board for
mfgtool download.Signed-off-by: Allen Xu
-
On imx6sx sabreauto, both QSPI1 and NAND would be mapped as mtd devices,
since we have already set the kernel to load QSPI1 first, the mtd index
for NAND need to be changed.Signed-off-by: Allen Xu
12 Nov, 2014
1 commit
-
Add 14x14 arm2 nand support
Signed-off-by: Frank Li
11 Nov, 2014
2 commits
-
Since we use WDOG_B reset now, we have to clear WDOG3 Power Down Enable
bit to avoid system reboot during normal kernel boot.
For mx6sxsabresd board, we have to make sure pad setting for WDOG_B ready
before mux ready, otherwise also cause reboot. But that dependes on hardware
design, only need on mx6sxsabresd board.Signed-off-by: Robin Gong
(cherry picked from commit 26875f93ac7e84748fa63e5f0dd948d12e663e43) -
Changed the QSPI PAD setting, the previous output drive strength is too
strong.Signed-off-by: Allen Xu
(cherry picked from commit 9dfb4a5ee01740eadb751ca5c9edfbec6f5059e3)
06 Nov, 2014
1 commit
-
MX6SX sabreauto board has analog video input from VADC. Add the GIS
support for this board that video input can display on LVDS at booting.The environment variable "gis" must be set to "vadc" to enable the function.
Signed-off-by: Ye.Li
(cherry picked from commit 5f2008a6dc08f07d462a063a0642f5e54fedbd21)
24 Oct, 2014
3 commits
-
Since the qspi2_clk_root is the root clock of u_gpmi_bch_input_gpmi_io_clk,
before switching the parent of qspi2_clk_root, we must gate off it.Signed-off-by: Ye.Li
-
For NAND boot, the kernel zImage and rootfs also need to load from
NAND. Add the environment variables for this.Signed-off-by: Ye.Li
-
Fix the GPIO assignments as per the board schematics.
Signed-off-by: Richard Zhu
23 Oct, 2014
1 commit
-
supported NAND boot on 19x19 ARM2 board.
Signed-off-by: Allen Xu
22 Oct, 2014
1 commit
-
The bootdata.size should contain the IVT offset part, but the calculation
for bootdata.size in imximage tool does not. This will cause some data at
the end of image not be loaded into memory.Signed-off-by: Ye.Li
20 Oct, 2014
3 commits
-
The MAX7322 will fail to work on 19x19 arm2 revB board. This failure
is caused by the MAX7322 reset pin is not released when calling the
setup_fec function.The MAX7322 reset pin is same as PHY reset pin. This patch fixes the issue
by moving the PHY reset from setup_iomux_fec1 to setup_fec.Signed-off-by: Ye.Li
-
The MAX7310 uses I2C3 bus. At system initialization, enable the driver to:
1. Reset CPU_PER_RST_B signal
2. Set the steering for ENET
3. Enable the LVDS displaySigned-off-by: Ye.Li
-
When set the pinmux to I2C functionality, the SION is required to enabled.
Signed-off-by: Ye.Li
11 Oct, 2014
1 commit
-
The PHY reset on 19x19 arm2 board is GPIO6_18, not GPIO4_22.
This causes the ethernet phy failed to work.Signed-off-by: Ye.Li
09 Oct, 2014
4 commits
-
Add android fastboot, recovery and booti support for mx6sx sabreauto board.
Signed-off-by: Ye.Li
-
Set the correct bmode value for booting from SDA/SDB/QSPI1/NAND
Signed-off-by: Ye.Li
-
define CONFIG_SPI_FLASH_BAR in mx6sx_arm2.h mx6sxsabreauto.h to
enable access to flash array higher than 16MB.CONFIG_SPI_FLASH_BAR is also set in mx6sxsabresd.h for RevB board.
Actually, if QSPI flash size
-
By introducing CONFIG_SPI_FLASH_BAR and add related command in LUT to
enable fsl_qspi.c can handle flash size bigger that 16M. Because uboot
does not support 32bits address access, this means bank address should
be used to access bigger flash.It is hard to let qspi driver dynamically set LUT, so BRRD BRWR RDEAR
and WREAR are all supported.Signed-off-by: Peng Fan
08 Oct, 2014
1 commit
-
OPCODE_BE_4K is supported. To qspi flashes which support 4k sector
erase, spi framework will use OPCODE_BE_4K command. Thus add this
support to let uboot can erase such qspi flashes.Signed-off-by: Peng Fan
30 Sep, 2014
1 commit
-
enable ldo-bypass check on all mx6sxsabresd boards.
Signed-off-by: Robin Gong
29 Sep, 2014
1 commit
-
The mx6sx sabreauto boards uses 2G DDR3. Modify the configuration
PHYS_SDRAM_SIZE to this size.Signed-off-by: Ye.Li
Acked-by: Jason Liu
26 Sep, 2014
2 commits
-
Create mx6sx sabreauto BSP file and configurations. The devices below
have been supported:1. SD/MMC/eMMC on SDA/SDB (base board) sockets
2. USB OTG port and USB HOST port (base board)
3. NAND flash
4. QuadSPI flash on QSPI1
5. I2C
6. PMIC PFUZE100
7. Onboard ethernet chip on ENET2
8. Splash screen on LVDSSigned-off-by: Ye.Li
-
Add support for i.MX6SX 14x14 lpddr2 arm2 board, same
as 17x17 arm2 except lpddr2 instead of ddr3.Signed-off-by: Nitin Garg
25 Sep, 2014
1 commit
-
Currently, flash quad bit is set in "spi_flash_validate_params" and later
at the end in the same api, we write 0 to status register for few flashes,
thereby overriding the quad bit set. This fix moves the quad bit setting
outside this api in "spi_flash_probe_slave"Signed-off-by: Sourav Poddar
Reviewed-by: Jagannadha Sutradharudu Teki
23 Sep, 2014
1 commit
-
ROM fixes the WEIM plugin issue in TO 1.2. The work around for hacking WEIM base
address to ROM variable is not needed. To avoid hacking useful data, remove the
work around for TO 1.2 and higher revisions.Signed-off-by: Ye.Li
18 Sep, 2014
6 commits
-
As M4 is sourcing UART clk from OSC, to make UART work
when M4 is enabled, need to select OSC as clk parent,
24M OSC is enough for debug UART in uboot.Signed-off-by: Anson Huang
-
Set the CONFIG_MXC_GPT_HCLK configuration in mx6_common.h, so that
enable the 24Mhz OSC GPT on all MX6 platforms.Signed-off-by: Ye.Li
-
For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the
preclk setting with kernel.Signed-off-by: Ye.Li
-
For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix
the get_ipg_per_clk function to support it.Signed-off-by: Ye.Li
-
The MX6SL has the perclk_clk_sel to select the perclk source. Add
its define in CCMSigned-off-by: Ye.Li
-
Introduce a new configuration "CONFIG_MXC_GPT_HCLK". When it is set,
the GPT will use 24Mhz OSC as clock source. Otherwise, the GPT will
use 32Khz OSC as clock source.Since only the GPT on iMX6 series provide the clock source option for
24Mhz OSC. For other series(MX5), if the configuration is set, the
perclk will be selected as clock source.MX6Q/D Rev 1.0 and MX6SL can't use the 24Mhz OSC clock source option,
so select the perclk for them. For MX6SL, we will set the OSC 24Mhz to
perclk in CCM, so eventually the clock comes from OSC 24Mhz.Signed-off-by: Ye.Li
11 Sep, 2014
1 commit
-
The self-bias circuit is used by the bandgap during startup.
Once the bandgap has stabilized, the self-bias circuit should be
disabled for best noise performance of analog blocks.
Also this bit should be disabled before the chip enters STOP mode or
when ever the regular bandgap is disabled.Signed-off-by: Ranjani Vaidyanathan
10 Sep, 2014
1 commit
-
THe anatop registers structure is duplicated with CCM structure at
PLL fields.
Since we are suggested not to use the name "anatop" any longer, merge
the anatop registers to the CCM structure "mxc_ccm_reg" and use CCM
to replace anatop.Signed-off-by: Ye.Li
05 Sep, 2014
2 commits
-
This problem is found when debugging QuadSPI. When "A" bit is enabled,
unaligned access will cause data abort exception. Actually, we do not
want this exception. So clear the align bit for MX6 SOCs.Tested this code with android team colleague and did not find problem.
Signed-off-by: Peng Fan
-
To fsl_qspi_write_data and fsl_qspi_ip_read, pointer txbuf and
rxbuf are not guaranteed that they are 4 Bytes aligned. Also,
it it not a good idea to cast type 'u8 *' to 'u32 *', except
we are sure that pointer type 'u8 *' is 4 Bytes aligned and
cast it to 'u32 *' will not pass memory boundary.The problem is found when using fsl_qspi_write_data to write
registers in flash devices. The err msg:data abort
pc : [] lr : []
sp : bf5512c8 ip : 0000001c fp : bf856608
r10: 87868904 r9 : bf551efc r8 : 200f048c
r7 : 00000002 r6 : bf551336 r5 : bf552a70 r4 : 00000001
r3 : 00000000 r2 : 00000060 r1 : 8783b520 r0 : 8783b520
Flags: nZCv IRQs on FIQs off Mode SVC_32
Resetting CPU ...The asm code which cause data abort is:
87822f30: e5964000 ldr r4, [r6]
From the dump msg, r6 is not 4 Bytes aligned, and data abort exception.So, Use mempcy but not unsafe type casting.
In this patch, max_write_size is assigned using txfifo to avoid possible
errors in future.Signed-off-by: Peng Fan
04 Sep, 2014
1 commit
-
Couple of issues in commit 21a2eb5f. The RAM size is wrong and
max number of DCD is 220.Signed-off-by: Nitin Garg
02 Sep, 2014
1 commit
-
WDZST bit is write-once only bit. So we need take care the setting
in kernel ,otherwise, kernel setting will never be enabled.Signed-off-by: Robin Gong
30 Aug, 2014
1 commit
-
The QSPI clock rate was set without disabling the clock gate, the
randomly glitch may mess up the clock and there will be no clock output,
when kernel boot up the QSPI access will fail.To debug this issueon i.MX6SX SDB, changed the u-boot bootscript to 'sf probe; reset'
to keep rebooting, the issue can be reproduced in 20 mins, set clock out
register in CCM and measured TP86, found there is no clock ouput.To fix this bug, disable clock gate before changing clock rate.
NOTICE: QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, need
to disable both of them.Signed-off-by: Allen Xu