13 Jan, 2014

8 commits

  • Tom Rini
     
  • Before this change ums mode can not be entered when device
    was using the same usb port for usb/uart communication.
    Switching USB cable from UART to USB always causes ums exit.

    Signed-off-by: Przemyslaw Marczak

    Przemyslaw Marczak
     
  • Arndale board has AX88760, which is USB 2.0 Hub & USB 2.0 Ethernet Combo
    controller, connected to HSIC Phy of USB host controller via USB3503 hub.

    This patch uses board specific board_usb_init function to perform reset
    sequence for USB3503 hub and enables the relevant config options for
    network to work.

    Signed-off-by: Inderpal Singh
    Signed-off-by: Chander Kashyap

    Inderpal Singh
     
  • The controller has 3 ports. The port0 is for USB 2.0 Phy, port1 and port2
    are for HSIC phys. The usb 2.0 phy is already being setup. This patch
    sets up the hsic phys.

    Signed-off-by: Inderpal Singh

    Inderpal Singh
     
  • The fifo size of ep0 is 64 bytes, and if the packet size grater than
    64 bytes, the driver would have to fill up the fifo multiple times,
    and before filling up the fifo, the driver should make sure the fifo
    is empty by checking fifo empty indication.

    However there is a hardware bug that the fifo empty indication is
    somehow a bit earlier than fifo reset. So if I don't add an extra
    delay here, the data might be corrupted. (i.e., 1 byte missing)

    After a couple of tests, it truns out that 1 usec is good enough.

    This workaround should be applied to all hardware revisions.

    Signed-off-by: Kuo-Jung Su
    CC: Marek Vasut

    Kuo-Jung Su
     
  • Since hardware revision 1.11.0, the following interrupt status
    registers are now W1C (i.e., write 1 clear):

    1. Interrupt Source Group 0 Register (0x144) (EP0 Abort: BIT5)
    2. Interrupt Source Group 2 Register (0x14C) (All bits)

    And before revision 1.11.0, these registers are all R/W.
    Which means software must write a 0 to clear the status.

    Signed-off-by: Kuo-Jung Su
    CC: Marek Vasut

    Kuo-Jung Su
     
  • The array reserved as a placeholder in the structure ipu_idmac
    should contain 44 32bit unsigned integer entries instead of 45
    ones, because the placeholder is located bewteen the register
    IDMAC_SC_CORD1 and the register IDMAC_CH_BUSY_1 with the address
    offsets of 0x804c and 0x8100 respectively.

    Reported-by: Robin Gong
    Acked-by: Robin Gong
    Cc: Stefano Babic
    Signed-off-by: Liu Ying

    Liu Ying
     
  • The array reserved1 as a placeholder in the structure ipu_cm
    should contain 4 32bit unsigned integer entries instead of 16
    ones, because the placeholder is located bewteen the register
    IPU_CH_DB_MODE_SEL_1 and the register IPU_ALT_CH_DB_MODE_SEL_0
    with the address offsets of 0x154 and 0x168 respectively.

    Reported-by: Robin Gong
    Acked-by: Robin Gong
    Cc: Stefano Babic
    Signed-off-by: Liu Ying

    Liu Ying
     

10 Jan, 2014

32 commits