14 Aug, 2015

3 commits


13 Aug, 2015

4 commits

  • The default boot command searches for dofastboot varaiable
    and does a fastboot if it is set to 1.
    But the condition "if test ${dofastboot} -eq 1" always
    returns true if dofastboot is not defined and breaking mmc boot.
    So make dofastboot as 0 by default and let the runtime
    environment set it if fastboot is required.

    Signed-off-by: Lokesh Vutla

    Lokesh Vutla
     
  • DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet
    provided IODELAY values for standard RGMII phys do not work.

    Silicon Revision(SR) 2.0 provides an alternative bit configuration
    that allows us to do a "gross adjustment" to launch the data off a
    different internal clock edge. Manual IO Delay overrides are still
    necessary to fine tune the clock-to-data delays. This is a necessary
    workaround for the quirky ethernet Phy we have on the platform.

    NOTE: SMA registers are spare "kitchen sink" registers that does
    contain bits for other workaround as necessary as well. Hence the
    control for the same is introduced in a generic SoC specific, board
    generic location.

    Signed-off-by: Nishanth Menon

    Nishanth Menon
     
  • Silicon revision 2.0 has new signal routing hence has an updated set of
    iodelay parameters to be used. Update the configuration for the same.
    Padmux remains the same.

    Based on data from VayuES2_EVM_Base_Config-20150807.

    NOTE: With respect to the RGMII values, the Manual IODelay values
    are used for the fine adjusments needed to meet the tight RGMII
    specification.

    Signed-off-by: Nishanth Menon

    Nishanth Menon
     
  • For am43xx_rtconly_evm_defconfig, the bootloader indicates support for
    RTC-Only modes by writing a magic number into RTC scratch register
    which kernel PM code will then clear and then write back again if
    RTC-Only mode entry is desired. If no PM code is loaded in the kernel,
    this magic number will not get cleared and then be detected again
    by the bootloader on a warm reboot, indicating an RTC+DDR resume event
    and causing the bootloader to attempt to jump to the resume address in
    RTC scratch register 0, which is invalid.

    Add a check to prevent jumping to address 0 if the scratch register is
    not properly programmed, otherwise warm reboot will not work on am437x
    if no PM is loaded in the kernel.

    Signed-off-by: Dave Gerlach

    Dave Gerlach
     

12 Aug, 2015

2 commits

  • ARM supported speeds and init value of core_pll for SDP1200
    are programmed wrong as part for the device speed cleanups.
    Fixing it here.

    Signed-off-by: Lokesh Vutla

    Lokesh Vutla
     
  • On keystone2 Lamarr and Edison platforms, the PA clocksource
    mux in PLL REG1, can be changed only after enabling its clock
    domain.
    So selecting the output of PASS PLL as input to PA only after
    enabling the clockdomain.
    This is as per the debug done by "Vitaly Andrianov "
    and based on the previous work done by "Hao Zhang "

    Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
    Reported-by: Vitaly Andrianov
    Tested-by: Vitaly Andrianov
    Signed-off-by: Lokesh Vutla

    Lokesh Vutla
     

07 Aug, 2015

19 commits


06 Aug, 2015

2 commits


05 Aug, 2015

10 commits