08 May, 2020
1 commit
09 Apr, 2020
1 commit
25 Nov, 2019
1 commit
15 Nov, 2019
1 commit
11 Nov, 2019
1 commit
03 Nov, 2019
1 commit
01 Nov, 2019
1 commit
18 Apr, 2019
1 commit
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initialize potential uninitialized variable with the type of"char*" to
be NULL in AVB. That "hashtree_error_mode" in code is manually specified
with a known value, the cases listed cover all potential value of
"hashtree_error_mode"explicitly do a type cast for memcpy parameters.
Change-Id: Ie5d234422a273d6dab75585bd0d8eb81583707ca
Signed-off-by: faqiang.zhu
11 Apr, 2019
4 commits
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Reserve 32M memory for GPU on AIY 1G DDR board.
Change-Id: I566a4a027982c8d4e41f280162f2f3cd67f1f5cd
Signed-off-by: Ji Luo -
* The default configuration (via resistor stuffing) is DFP (host). This
means that on Type-C hosts fastboot won't work.
* Set to UFP to ensure fastboot works properly.Change-Id: I2b63d95e08df70da43dee1f8f7bb59d1863943f4
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* There is an enumeration problem when using superspeed.
* This doesn't fix it with all hubs, but can enable fastboot to work on
some 3.0 hosts.Change-Id: If4a603126b945bd8f84c3d6e975e1185530eb193
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* Bucks 1-4 will be reconfigured via DVS in the kernel.
* Buck 5 is explicitly set to 1.0V
* Regulator lock/unlock is added, this ensures that in warm or cold
reset the values will be set.Change-Id: I8d8be74bddbbd081030fe1762b9f9c6534c7fb77
01 Apr, 2019
1 commit
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Add support for DVT AIY 1G board, distinguish the board type
with the board id.
TYPE: ID:
Micron 1G 0x5
HYNIX 1G 0x3
Micron 3G 0x1Test: Boot on AIY 1G/3G ddr board.
Change-Id: I3c7b6ebe8bc5d4e59917fcc3947e9ebfefc940da
Signed-off-by: Ji Luo
21 Mar, 2019
1 commit
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previous setting can NOT meet the USB stream mode performance settting.
So use the default QoS setting on the i.MX8MM DDR4.Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
(cherry picked from commit dc9b5e2ffb1d74477c7ec766c6312f9e98afa64c)
18 Mar, 2019
1 commit
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Update the lpddr4 timing config to align with the ddr tool
Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
(cherry picked from commit a1433dec3a03a6c944b61600e7b317e2a83f2981)
26 Feb, 2019
3 commits
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When flexspi is assigned to M4 for XIP, its power up/down will fail.
This is expected so don't need to give warning.Signed-off-by: Ye Li
(cherry picked from commit 0803b4a9d4074a5bb101d194633cbdd7510a1e9a) -
The CONFIG_QSPI_BOOT has been removed from SPL flexspi build, because
we have to change the u-boot ENV to SD/MMC, and this configuration will
set relevant configurations.But we don't clean up CONFIG_QSPI_BOOT for SPL completely, SPL still has
some places using it and cause problem to flexspi boot.
Using CONFIG_SPL_SPI_SUPPORT to replace the CONFIG_QSPI_BOOT.Signed-off-by: Ye Li
(cherry picked from commit 0491bd4ba21ad620b4c514323a7d6b8a9e10325c) -
Update the ddr training code to work with the atf 2.0.
Test: Build and boot on imx8mq aiy 3G board.
Change-Id: I8546c34cfa4aeeed819f7797f8362676e420b41f
Signed-off-by: Ji Luo
25 Feb, 2019
1 commit
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When M4 is booted by ROM, we have to enable RPMSG in kernel, so need
to select the -rpmsg.dtb. If M4 is not enabled, use default kernel dtb.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 8a57be45e18295ce1b19799723775cf5b205281d)
12 Feb, 2019
1 commit
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Since we have asked SCFW to do this job to avoid issues in partition
reboot, remove relevant codes.Signed-off-by: Ye Li
(cherry picked from commit 8128566e843d76720cdc5c3e075fa303e401132f)
11 Feb, 2019
1 commit
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According to latest datasheet IMX8MMCEC_Rev_0, the typical voltage
of VDD_DRAM for 1.5GHz DDR clock is 0.95v. Because BD71847MWV PMIC
does not support 0.95v output. We change the voltage to 0.975v as
the note in datasheet mentioned it is acceptable and supported.Signed-off-by: Ye Li
Reviewed-by: Bai Ping
25 Jan, 2019
2 commits
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SCFW has taken to reset the base board by deasserting BB_PER_RST_B(SCU_GPIO0_01) on
imx8QM MEK board, and has removed the SC_R_BOARD_R1 functionality.
So We don't need to explicitly use SC_R_BOARD_R1, delete the codes from u-boot.Signed-off-by: Ye Li
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There are two new validation boards: LPDDR4 board (30123) and DDR3L board (30010)
for imx8x family 17x17 chips. These two boards have same design except the DDR.
Since SCFW is resposible for DDR initialization, U-boot could use one build to
cover two boards.
The 8DX 17x17 DDR3L ARM2 has been added into u-boot before, so we rename the config
CONFIG_TARGET_IMX8DX_DDR3_ARM2 to CONFIG_TARGET_IMX8X_17X17_VAL to cover DDR3L and
LPDDR4.Considering 8DX and 8QXP 17x17 may solder to the boards, we create two defconfig:
one for DX and another for 8qxp to share with the CONFIG_TARGET_IMX8X_17X17_VAL
but with different FDTs.Signed-off-by: Ye Li
21 Jan, 2019
2 commits
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According to the latest datasheet, software is expected to program
the VDD_SOC voltage to the typical value 0.85V prior to the first
DRAM memory access. At default the VDD_SOC is 0.8V from PMIC BUCK1,
so we have to change it to 0.85V in SPL.Signed-off-by: Ye Li
Tested-by: Anson Huang -
Enable the new mipi panel driver and add parameters to board codes.
We enable the RM68200_WXGA as default panel, users can set "panel"
environment variable to switch to different panel.Signed-off-by: Ye Li
Reviewed-by: Fancy Fang
09 Jan, 2019
2 commits
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Enable the SPL SDP driver and USB driver in MEK board codes and defconfigs.
Because the USB driver needs larger malloc pool, increase the malloc size
and disable simple mallocSigned-off-by: Ye Li
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The SPL won't use host mode, and the tcpc is default set as device mode.
So we don't need to access tcpc in SPL.Signed-off-by: Ye Li
26 Dec, 2018
1 commit
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Since the gpio non-dm driver maps to wrong GPIO register, the SPL
also powers up wrong GPIO resources.Signed-off-by: Ye Li
Acked-by: Peng Fan
20 Dec, 2018
2 commits
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The HAB code can not set Field Return and SRK Revoke sticky bits in case
OCOTP CTRL clock is gated out.In case we disable OCOTP CTRL clock in DCD and plugin those features may
not operate as expected.Keep OCOTP CTRL clock enabled in DCD and plugin so HAB can propely lock
those features, users should use the CSF Unlock command to prevent those
features from being locked.Signed-off-by: Breno Lima
Reviewed-by: Ye Li -
The HAB code can not set Field Return and SRK Revoke sticky bits in case
OCOTP CTRL clock is gated out.In case we disable OCOTP CTRL clock in DCD and plugin those features may
not operate as expected.Keep OCOTP CTRL clock enabled in DCD and plugin so HAB can propely lock
those features, users should use the CSF Unlock command to prevent those
features from being locked.Signed-off-by: Breno Lima
18 Dec, 2018
1 commit
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Keep high speed for SPL, but for normal uboot, enable super speed.
Reviewed-by: Ye Li
Reviewed-by: Peter Chen
Tested-by: faqiang.zhu
Signed-off-by: Li Jun
12 Dec, 2018
2 commits
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Write magic number in board early init, and clear magic when booting
Linux.This is to let XEN know the current EL1 code is U-Boot or Linux
when reset/reboot. This is just a workaround because CM41 could not
communicate with XEN now, even XEN knows that EL1 is reseting/rebooting.Signed-off-by: Peng Fan
Reviewed-by: Flynn xu -
To support partition reboot, the u-boot has to enable clocks by LPCG.
The LPCG will reset to default value only when the subsystem is totally
power off and reset. However, the resources in one subsystem may belong
to different partitions, so the partition reboot may not reboot the entire
subsystem.
Powers, clocks/lpcg, GPR, IP may not reset depends on various cases and
HW design. Thus, AP software has to ensure everything is reset by SW
itself to support such above cases.Signed-off-by: Ye Li
26 Nov, 2018
1 commit
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Add support for new target imx8mq_aiy.
Test: build and boot ok on imx8mq_aiy.
Change-Id: I7bb8b66e5235a7122073dcfb4cdc7f165036b9a6
Signed-off-by: Ji Luo
20 Nov, 2018
1 commit
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Update the ddrc Qos setting for B1 to align with B0'ssetting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.Signed-off-by: Bai Ping
Reviewed-by: Ye Li
Tested-by: Robby Cai
12 Nov, 2018
5 commits
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- temp fix for boot hangup with camera
This reverts commit a8109598e7dca72d415ad5d26ac5868b88da9dfc.
Bug: 115532706
Test: test boot up
Change-Id: I7bb1bc14eb81ae0965fc03abdf5cb65444720d13 -
Add fastboot commands "fastboot oem at-get-vboot-unlock-challenge"
and "fastboot oem at-unlock-vboot" to support the authenticated
unlock feature for Android Things devices. Use software random
numbers generator to generate the 16 bytes random challenge, it
should be replaced with hardware encrypted random generator when
the TEE part is ready.Test: Generate unlock challenge by:
./avbtool make_atx_unlock_credential
--output=atx_unlock_credential.bin
--intermediate_key_certificate=atx_pik_certificate.bin
--unlock_key_certificate=atx_puk_certificate.bin
--challenge=my_generated_challenge.bin
--unlock_key=testkey_atx_puk.pem
validated the unlock credential successfully on imx7d_pico
and AIY.Change-Id: I4b8cee87c9e96924169479b65020a081136681f6
Signed-off-by: Ji Luo -
Trusty image should be loaded to different address for AIY 1G/3G ddr
board which have different ddr size. Use board id to distinguish
different baseboard, load trusty image to 0x7e00_0000 for AIY 1G ddr
board and 0xfe00_0000 for AIY 3G ddr board.Test: build and boot Trusty ok for AIY 1G/3G ddr board.
Change-Id: I62d8a19b13fe19f38075512a6faa4bbb36f74791
Signed-off-by: Ji Luo -
Because sysdeps.h in trusty include stdint.h, so we need to define
USE_STDINT.Test: Local build test and flash on imx7d. Verify provision som
key and product key succeed.
Bug: None
Change-Id: I08db7c10dd4453a87f15ff4432335fe4c41f9c5f -
for 1GB ram: cma=296M galcore.contiguousSize=8388608
for 3GB ram: cma=384M
Test: Boot successfully on AIY-1G & AIY-3GChange-Id: If082d5b751b5a5e06efe301c0b8e49ec4ac3dfb7
Signed-off-by: faqiang.zhu
Reviewed-on: http://androidsource.ap.freescale.net/project/5262
Reviewed-by: Wang Haoran
Signed-off-by: faqiang.zhu
