Eric Lee / smarc-uboot

06 Apr, 2016

1 commit

03 Jan, 2016

1 commit

  • f0b5f23f3   ARM: imx: fsl_esdhc: fix usage of low 4 bits of sysctl register ... Browse Code »

    The low four bits of the SYSCTL register are reserved on the USDHC
    controller on i.MX6 and i.MX7 processors, but are used for clocking
    operations on earlier models.

    Guard against their usage by hiding the bit mask macros on those
    processors.

    These bits are used to prevent glitches when changing clocks on
    i.MX35 et al. Use the RSTA bit instead for i.MX6 and i.MX7.

    >From the i.MX6DQ RM:
    To prevent possible glitch on the card clock, clear the
    FRC_SDCLK_ON bit when changing clock divisor value(SDCLKFS
    or DVS in System Control Register) or setting RSTA bit.

    Signed-off-by: Eric Nelson
    Reviewed-by: Fabio Estevam
    Reviewed-by: Stefano Babic
    Reviewed-by: Hector Palacios

    Eric Nelson
     

30 Oct, 2015

1 commit

05 May, 2015

2 commits

  • 2d9ca2c72   mmc: fsl_esdhc: Add peripheral clock support ... Browse Code »
    12

    The SD clock could be generated by platform clock or peripheral
    clock for some platforms. This patch adds peripheral clock
    support for T1024/T1040/T2080. To enable it, define
    CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK.

    Signed-off-by: Yangbo Lu
    Cc: York Sun
    Cc: Pantelis Antoniou
    Reviewed-by: York Sun

    Yangbo Lu
     
  • 5a8dbdc6b   mmc: fsl_esdhc: Add adapter card type identification support ... Browse Code »

    Add adapter card type identification support by reading
    FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function,
    define CONFIG_FSL_ESDHC_ADAPTER_IDENT.

    Signed-off-by: Yangbo Lu
    Cc: York Sun
    Cc: Pantelis Antoniou
    [York Sun: resolve conflicts in README.fsl-esdhc]
    Reviewed-by: York Sun

    Yangbo Lu
     

24 Apr, 2015

1 commit

02 Mar, 2015

1 commit

25 Feb, 2015

1 commit

23 Feb, 2015

1 commit

09 Sep, 2014

1 commit

23 Apr, 2014

1 commit

24 Mar, 2014

1 commit

  • 93bfd6167   mmc: Split mmc struct, rework mmc initialization (v2) ... Browse Code »

    The way that struct mmc was implemented was a bit of a mess;
    configuration and internal state all jumbled up in a single structure.

    On top of that the way initialization is done with mmc_register leads
    to a lot of duplicated code in drivers.

    Typically the initialization got something like this in every driver.

    struct mmc *mmc = malloc(sizeof(struct mmc));
    memset(mmc, 0, sizeof(struct mmc);
    /* fill in fields of mmc struct */
    /* store private data pointer */
    mmc_register(mmc);

    By using the new mmc_create call one just passes an mmc config struct
    and an optional private data pointer like this:

    struct mmc = mmc_create(&cfg, priv);

    All in tree drivers have been updated to the new form, and expect
    mmc_register to go away before long.

    Changes since v1:

    * Use calloc instead of manually calling memset.
    * Mark mmc_register as deprecated.

    Signed-off-by: Pantelis Antoniou

    Pantelis Antoniou
     

21 Aug, 2013

1 commit

  • bb0dc1084   powerpc: mpc85xx: Support booting from SD Card with SPL ... Browse Code »

    The code from the internal on-chip ROM. It loads the final uboot image
    into DDR, then jump to it to begin execution.

    The SPL's size is sizeable, the maximum size must not exceed the size of L2
    SRAM. It initializes the DDR through SPD code, and copys final uboot image
    to DDR. So there are two stage uboot images:
    * spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that
    ddr spd code can get the interleaving mode setting in env. It loads
    final uboot image from offset 96KB.
    * final uboot image, size is variable depends on the functions enabled.

    Signed-off-by: Ying Zhang
    Acked-by: York Sun

    Ying Zhang
     

24 Jul, 2013

1 commit

14 Apr, 2013

1 commit

  • 9b74dc56f   fsl_esdhc: Fix DMA transfer completion waiting loop ... Browse Code »

    Rework the waiting for transfer completion loop condition
    to continue waiting until both Transfer Complete and DMA End
    interrupts occur. Checking of DLA bit in Present State register
    looks not needed in addition to interrupts status checking,
    so it can be removed from the condition. Also, DMA Error
    condition is added to the list of data errors, checked in the loop.

    Signed-off-by: Andrew Gabbasov

    Andrew Gabbasov
     

03 Apr, 2013

1 commit

  • aad4659a2   mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a board ... Browse Code »

    Maximum bus width supported by some i.MX6 boards is not 8bit like
    others. In case where both host controller and card support 8bit transfers,
    they agree to communicate on 8bit interface while some boards support only 4bit interface.
    Due to this reason the mmc 8bit default mode fails on these boards. To rectify this,
    define maximum bus width supported by these boards (4bit). If max_bus_width is not
    defined, it is 0 by default and 8bit width support will be enabled in host
    capabilities otherwise host capabilities are modified accordingly.

    It is tested with a MMCplus card.

    Signed-off-by: Abbas Raza
    cc: stefano Babic
    cc: Andy Fleming
    Acked-by: Dirk Behme
    Acked-by: Andrew Gabbasov

    Abbas Raza
     

16 Oct, 2012

1 commit

  • a2ac1b3a7   mxc: Fix SDHC multi-instance clock ... Browse Code »

    On mxc, each SDHC instance has a dedicated clock, so gd->sdhc_clk is not
    suitable for the multi-instance use case (initialization made directly with
    fsl_esdhc_initialize()).

    This patch fixes this issue by adding a configuration field for the SDHC input
    clock frequency.

    Signed-off-by: Benoît Thébaudeau
    Cc: Stefano Babic
    Cc: Eric Bénard
    Cc: Otavio Salvador
    Cc: Fabio Estevam
    Cc: Jason Liu
    Cc: Matt Sealey
    Cc: Andy Fleming

    Benoît Thébaudeau
     

01 Sep, 2012

1 commit

  • 16e43f354   fsl_esdhc: Remove cache snooping for i.MX ... Browse Code »

    The cache snooping feature of Freescale's eSDHC IP is not available on i.MX, so
    disable it globally for this architecture. This avoids setting no_snoop for all
    i.MX boards, and it prevents setting a reserved bit of a reserved register if
    fsl_esdhc_mmc_init() is used on i.MX, like in
    arch/arm/cpu/armv7/imx-common/cpu.c/cpu_mmc_init().

    Since no_snoop was only used on i.MX, get rid of it BTW.

    Signed-off-by: Benoît Thébaudeau
    Cc: Andy Fleming
    Cc: Stefano Babic
    Cc: Kim Phillips

    Benoît Thébaudeau
     

09 May, 2012

1 commit

  • 7a5b80297   mmc: fsl_esdhc: Poll until card is not busy anymore ... Browse Code »

    This patch imports parts of two patches from the Freescale U-Boot with the following
    commit messages:

    ENGR00156405 ESDHC: Add workaround for auto-clock gate errata ENGcm03648
    http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/drivers/mmc/imx_esdhc.c?h=imx_v2009.08_12.01.01&id=e436525a70fe47623d346bc7d9f08f12ff8ad787
    The errata, not applicable to USDHC, causes ESDHC to shut off clock to the card
    when auto-clock gating is enabled for commands with busy signalling and no data
    phase. The card might require the clock to exit the busy state, so the workaround
    is to disable the auto-clock gate bits in SYSCTL register for such commands. The
    workaround also entails polling on DAT0 bit in the PRSSTAT register to learn when
    busy state is complete. Auto-clock gating is re-enabled at the end of busy state.

    ENGR00156670-1 ESDHC/USDHC: Remove delay before each cmd and some bug fixes
    http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/drivers/mmc/imx_esdhc.c?h=imx_v2009.08_12.01.01&id=a77c6fec8596891be96b2cdbc742c9824844b92a
    Removed delay of 10 ms before each command. There should not be a need to have this
    delay after the ENGR00156405 patch that polls until card is not busy anymore before
    proceeding to next cmd.

    This patch imports the polling part of both patches. The auto-clock gating code
    don't apply for i.MX6 as implemented in these two patches.

    SYSCTL_RSTA was defined twice. Remove one definition.

    Signed-off-by: Dirk Behme
    CC: Andy Fleming
    CC: Fabio Estevam
    CC: Stefano Babic

    Dirk Behme
     

11 Apr, 2011

1 commit

  • 32c8cfb23   fsl_esdhc: Deal with watermark level register related changes ... Browse Code »

    P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
    level register description has been changed:

    9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
    25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00

    Signed-off-by: Priyanka Jain
    Signed-off-by: Poonam Aggrwal
    Tested-by: Stefano Babic
    Signed-off-by: Kumar Gala

    Priyanka Jain
     

24 Apr, 2010

1 commit

07 Apr, 2010

3 commits

08 Mar, 2010

1 commit

26 Jan, 2010

1 commit

17 Jul, 2009

1 commit

  • b33433a63   fsl_esdhc: Add device tree fixups ... Browse Code »

    This patch implements fdt_fixup_esdhc() function that is used to fixup
    the device tree.

    The function adds status = "disabled" propery if esdhc pins muxed away,
    otherwise it fixups clock-frequency for esdhc nodes.

    Signed-off-by: Anton Vorontsov
    Acked-by: Kim Phillips

    Anton Vorontsov
     

17 Feb, 2009

1 commit