31 Aug, 2016
1 commit
23 Aug, 2016
1 commit
18 Aug, 2016
3 commits
17 Aug, 2016
1 commit
02 Jun, 2016
1 commit
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We should not depend on CONFIG_DRIVER_TI_CPSW to fixup PRU Ethernet
MAC addresses. Always fix them up.Signed-off-by: Roger Quadros
30 May, 2016
1 commit
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Commit 6ca5f482a38ce ("driver: net: cpsw: add support for RGMII id mode
support and RMII clock source selection") enables the external chip clock
for RMII mode using private data. This data needs to be populated from
DT data. The above commit misses populating this data.Signed-off-by: Lokesh Vutla
26 May, 2016
5 commits
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In commit c3839fc5b8e9 ("board: am335x: Always set eth/eth1addr environment variable")
we got rid of setting usbnet_devaddr based on efuse.However this causes SPL USB eth boot to fail as usbnet_devaddr is
not set. We bring back the code that sets usbnet_devaddr based on
efuse.Fixes: c3839fc5b8e9 ("board: am335x: Always set eth/eth1addr environment variable")
Signed-off-by: Roger Quadros
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Commit 6ca5f482a38ce ("driver: net: cpsw: add support for RGMII id mode
support and RMII clock source selection") missed update for am43xx variants.
Updating it here.Fixes: 6ca5f482a38ce ("driver: net: cpsw: add support for RGMII id mode support and RMII clock source selection")
Reported-by: Roger Quadros
Signed-off-by: Lokesh Vutla -
Enable CONFIG_CMD_TIME for all dra7xx platforms
Signed-off-by: Lokesh Vutla
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Enable CONFIG_CMD_TIME for all am57x platforms
Signed-off-by: Lokesh Vutla
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Enable CONFIG_CMD_TIME for all am43xx platforms
Signed-off-by: Lokesh Vutla
25 May, 2016
7 commits
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Enable CONFIG_CMD_TIME for all am335x platforms
Signed-off-by: Lokesh Vutla
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The index returned by get_sys_clk_index() is not exactly what we expect.
Let's not rely on that and use get_sys_clk_freq() instead.This fixes missing USB3 devices in the Linux kernel when USB is started
in u-boot. It still doesn't fix missing USB3 devices in u-boot though.Signed-off-by: Roger Quadros
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DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled
for USB1 instance in Super-Speed.Signed-off-by: Roger Quadros
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CONFIG_USB_XHCI_OMAP can be set for host mode without setting
CONFIG_USB_DWC3 which is meant for gadget mode only.
board_usb_init() was not being defined for CONFIG_USB_XHCI_OMAP
resulting in a data abort on usb start.Define board_usb_init() for CONFIG_USB_XHCI_OMAP case. Move
gadget specific handling to within CONFIG_USB_DWC3.Fixes: 6f1af1e358b7 ("board: ti: invoke clock API to enable and disable clocks")
Signed-off-by: Roger Quadros -
CONFIG_USB_XHCI_OMAP is enabled for host mode independent of CONFIG_USB_DWC3
which is meant for gadget mode only. We need enable/disbale_usb_clocks() for
host mode as well so provide for it.Fixes: 09cc14f4bcbf ("ARM: AM43xx: Add functions to enable and disable USB clocks"
Signed-off-by: Roger Quadros -
Now that we have driver model Ethernet driver
integrated, switch to using that instead of
unsupported legacy driver.Ethernet continues to work before and after this
patch on AM572x GP EVM.Signed-off-by: Sekhar Nori
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Now that we have AHCI driver integrated, switch
to use that instead of the unsupported legacy
driver.This fixes broken SATA support on AM572x GP EVM.
Signed-off-by: Sekhar Nori
23 May, 2016
3 commits
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Now the u-boot spi image is greater than 0x80000, increase the same
in env during spi erase.Reported-by: Yan Liu
Signed-off-by: Lokesh Vutla -
In the current driver implementation, config() callback is common
for AR8035 and AR8031 phy. In config() callback, driver tries to
configure MMD Access Control Register and MMD Access Address Data
Register unconditionally for both phy versions which leads to
auto negotiation failure in AM335x EVMsk second port which uses
AR8031 Giga bit RGMII phy. Fixing this by adding separate config
for AR8031 phy.Reviewed-by: Sekhar Nori
Signed-off-by: Mugunthan V N -
According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
throughput.Signed-off-by: Vignesh R
20 May, 2016
1 commit
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All the output clock parameters of a DPLL needs to be programmed before
locking the DPLL. But it is being configured after locking the DPLL which
could potentially bypass DPLL. So fixing this sequence.Reported-by: Richard Woodruff
Signed-off-by: Lokesh Vutla
19 May, 2016
6 commits
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This provides a way to load a FIT containing U-Boot and a selection of device
tree files from UART.Signed-off-by: Lokesh Vutla
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sectors field is not being updated when reading fdt from fit image. Because of
this size_of(u-boot.bin) is being read when reading fdt. Fixing it by updating
the sectors field properly.Signed-off-by: Lokesh Vutla
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No prints should be allowed during UART load.
Signed-off-by: Lokesh Vutla
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In AM335x GP EVM, Atheros 8031 phy is used, enable the driver as
AM335x SoC RGMII delay mode has to be enabled in phy as mentioned
in the silicon errata Advisory 1.0.10Signed-off-by: Mugunthan V N
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cpsw driver supports only selection of phy mode in control module
but control module has more setting like RGMII ID mode selection,
RMII clock source selection. So ported to cpsw-phy-sel driver
from kernel to u-boot.Signed-off-by: Mugunthan V N
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This is needed in case of am57xx where in board detection is done
pretty late in the init sequence. The pmic registers for variants
of am57xx are different hence we need to assign them carefully based
on the board type. Add a function to assign omap_vcores after the
board detection is done.Fixes: 888ea8611c1 ("ARM: dts: AM572x-IDK Initial Support")
Fixes: 1084ffa86a5 ("ARM: dts: AM571x-IDK Initial Support")
Reported-by: Suman Anna
Signed-off-by: Keerthy
17 May, 2016
1 commit
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* 'master' of git://git.denx.de/u-boot: (31 commits)
Prepare v2016.05
sunxi: Enable USB host in CHIP defconfig
test, tools: update tbot documentation
tests: py: fix NameError exception if bdi cmd is not supported
arm/arm64: Move barrier instructions into separate header
arm: socfpga: Update iomux and pll for c5 socdk RevE
warp7: Fix boot by selecting CONFIG_OF_LIBFDT
usb: gadget: dfu: discard dead code
dfu: avoid memory leak
usb: dwc2: Add delay to fix the USB detection problem on SoCFPGA
usb: hub: Don't continue on get_port_status failure
usb: Assure Get Descriptor request is in separate microframe
usb: Wait after sending Set Configuration request
socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabled
mtd: cqspi: Simplify indirect read code
mtd: cqspi: Simplify indirect write code
arm: socfpga: socrates: Add 'time' command
ARM: socfpga: Disable USB OC protection on SoCrates
usb: Don't init pointer to zero, but NULL
usb: ehci-mx6: allow board_ehci_hcd_init to fail
...Signed-off-by: Lokesh Vutla
16 May, 2016
1 commit
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Signed-off-by: Tom Rini
15 May, 2016
1 commit
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Reported-and-tested-by: Dennis Gilmore
Signed-off-by: Hans de Goede
Acked-by: Ian Campbell
13 May, 2016
6 commits
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update tbot documentation in U-Boot, as I just
merged the event system into tbots master
branch.Signed-off-by: Heiko Schocher
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test/py raises an error, if a board has not enabled bdi command
> pytest.skip('bdinfo command not supported')
E NameError: global name 'pytest' is not definedimport pytest in test/py/u_boot_utils.py fixes this.
Signed-off-by: Heiko Schocher
Reviewed-by: Stephen Warren -
The commit 539982820939 ("ARM: DRA7: Fixup DSPEVE and IVA clock
frequencies based on OPP") only updates the 'assigned-clock-rates'
property and expects that the 'assigned-clocks' property is already
defined in the existing DTBs. The kernel clock init configuration
logic requires both these properties to be defined in a clock
node inorder to properly update the clock frequencies. Enhance
the current frequency update logic to also add the 'assigned-clocks'
property so that the DSPEVE and IVA DPLLs are configured properly
even for kernels that do not have the OPP_NOM DPLL clock rate
configuration in the DTBs. The additional logic is a no-op for
kernels that do use DTBs with corresponding 'assigned-clocks'
property.Signed-off-by: Suman Anna
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The commit 539982820939 ("ARM: DRA7: Fixup DSPEVE and IVA clock
frequencies based on OPP") defined different clock rates for
DSP at OPP_HIGH between DRA75x/AM572x and DRA72x/AM571x family
of SoCs. The DRA72x OPP_HIGH clock rate was based on the current
DRA72x Data Manual. The OPP_HIGH clock rate for AM571x is though
defined to be as the same as the AM572x SoCs - 750 MHz. The DRA7xx
DMs will be updated soon to mark the highest supported frequency
as 750 MHz. So, fixup the DSP OPP_HIGH clock rate accordingly.
The clock rates are also consolidated since they are identical
across all the DRA75x/AM572x, DRA72x/AM571x family of SoCs.While at this, fix couple of minor typos, one a fix for the
IVA clock number macro in the IVA clock names definition, and
another a trace correction.Fixes: 539982820939 ("ARM: DRA7: Fixup DSPEVE and IVA clock frequencies based on OPP")
Signed-off-by: Suman Anna -
Now SPL will be able to select serial device dynamically, remove icev2
defconfig which is created to pass a separate serial device.Signed-off-by: Lokesh Vutla
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Different AM335x based platforms have different serial consoles. As serial
console is Kconfig option a separate defconfig has to be created for each
platform. So pass the serial device dynamically.Signed-off-by: Lokesh Vutla
12 May, 2016
1 commit
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Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory
barrier") broke compilation for the Pine64, as dram_helper.c now
includes , which does not compile on arm64.Fix this by moving all barrier instructions into a separate header
file, which can easily be shared between arm and arm64.
Also extend the inline assembly to take the "sy" argument, which is
optional for ARMv7, but mandatory for v8.This fixes compilation for 64-bit sunxi boards (Pine64).
Acked-by: Ian Campbell
Signed-off-by: Andre Przywara
