06 Oct, 2014
11 commits
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Enable the PL310 L2 cache controller support for the SoCFPGA.
With the cache related issues resolved, this is safe to be done.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
The Cortex-A9 has 32-byte long L1 cachelines. Define this value.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel MachekV2: Move the not-CPU specific stuff into drivers/fpga/ and base
this on the cleaned up altera FPGA support. -
The timer reload value is a property of the timer hardware and there
is no reason for this to be configurable. Place this into the timer
driver just like on the other hardware.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Dinh Nguyen
Acked-by: Pavel Machek -
Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel MachekV2: Fixed the L4 MP clock divider and synced the clock code with latest
rocketboards codebase (thanks Dinh for pointing this out) -
…ic/drivers/net-20141006', 'topic/tools/mkimage-20141006' and 'topic/arm/cache-20141006' into HEAD
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Like many platforms, the Altera socfpga platform requires that the
preloader be "signed" in a certain way or the built-in boot ROM will
not boot the code.This change automatically creates an appropriately signed preloader
from an SPL image.The signed image includes a CRC which must, of course, be generated
with a CRC generator that the SoCFPGA boot ROM agrees with otherwise
the boot ROM will reject the image.Unfortunately the CRC used in this boot ROM is not the same as the
Adler CRC in lib/crc32.c. Indeed the Adler code is not technically a
CRC but is more correctly described as a checksum.Thus, the appropriate CRC generator is added to lib/ as crc32_alt.c.
Signed-off-by: Charles Manning
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel MachekV2: - Zap unused constant
- Explicitly print an error message in case of error
- Rework the hdr_checksum() function to take the *header directly
instead of a plan buffer pointer -
Remove this symbol from configs, since it's unused.
Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Cc: Joe Hershberger
Acked-by: Chin Liang See -
The DMA descriptors used by the DW MMC block must be aligned to cacheline
size, otherwise we are unable to properly flush/inval cache over them and
we get data corruption.The reason I chose this approach of expanding the structure is because
the driver allocates the descriptors in bulk. This approach does waste
space by inserting slop inbetween the descriptors, but it makes access
to the descriptors easy as the compiler does know the real size of the
structure. It also makes cache operations easy, since the size of the
structure is cache aligned and the structure start address is as well.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Cc: Pantelis Antoniou
Acked-by: Pavel Machek -
Get rid of the line-over-80 problems and zap the typedef that
went alongside those enums.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek
27 Sep, 2014
3 commits
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Some of the #defines in spi.h are not bracketed. To avoid future mistakes
add brackets. Also add an explanatory comment for SPI_CONN_DUAL_...Signed-off-by: Simon Glass
Reviewed-by: Jagannadha Sutradharudu Teki -
Sandbox may as well support everything. This increases the amount of code
that is built/tested by sandbox, and also provides access to all the
supported SPI flash devices.Signed-off-by: Simon Glass
Reviewed-by: Jagannadha Sutradharudu Teki
26 Sep, 2014
3 commits
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LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.Signed-off-by: York Sun
CC: Alison Wang
25 Sep, 2014
23 commits
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When booting with SP, RCW resides at the beginning of IFC NOR flash.
Signed-off-by: York Sun
-
Spin table is at the very beginning of boot code. Each core has an individual
release address within the spin table, the ft_cpu_setup fn updates the
"cpu-release-addr" property of each cpu node with the corresponding release
address.Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.
Signed-off-by: York Sun
Signed-off-by: Arnab Basu -
of_bus_default_count_cells can be used to get the #address-cells
and #size-cells defined by the current node's parent node. This
is required when using of_read_number to read from FDT nodes that
can be 32 or 64 bytes depending on values defined by the parent.Signed-off-by: Arnab Basu
CC: Scott Wood -
This is being done so that it can be used outside 'fdt_support.c'. Making
life more convenient when reading device node properties that can be 32
or 64 bits long.Signed-off-by: Arnab Basu
Cc: Scott Wood -
The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 spec, remove tCKE as an config option.Signed-off-by: York Sun
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DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).Signed-off-by: York Sun
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U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.Signed-off-by: York Sun
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Add support of NOR and NAND flash for simulator target.
Here
IFC - CS0: NOR flash
IFC - CS1: NAND flashSigned-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
This option specifies the default Device Tree used for the run-time
configuration of U-Boot.Signed-off-by: Masahiro Yamada
Cc: Simon Glass
Cc: Stephen Warren
Cc: Minkyu Kang
Cc: Michal Simek -
This commit moves:
CONFIG_OF_CONTROL
CONFIG_OF_SEPARATE
CONFIG_OF_EMBED
CONFIG_OF_HOSTFILEBecause these options are currently not supported for SPL,
the "Device Tree Control" menu does not appear in the SPL
configuration.Note:
zynq-common.h should be adjusted so as not to change the
default value of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME.Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
Cc: Stephen Warren
Cc: Minkyu Kang
Acked-by: Michal Simek -
The libc headers on FreeBSD and likely related projects as well contain an
header file, cdefs.h which provides similiar functionality as linux/compiler.h.
It provides compiler independent defines like __weak __packed, to allow
compiling with multiple compilers which might have a different syntax for such
extension.Since that header file is included in multiple standard headers, like stddef.h
and stdarg.h, multiple definitions of those defines will be present if both are
included. When compiling u-boot the compiler will warn about it hundreds of
times since e.g. common.h will include both files indirectly.commit 7ea50d52849fe8ffa5b5b74c979b60b1045d6fc9 "compiler_gcc: do not redefine
__gnu_attributes" prevented such redefinitions, but this was undone by commit
fb8ffd7cfc68b3dc44e182356a207d784cb30b34 "compiler*.h: sync
include/linux/compiler*.h with Linux 3.16".Add the checks back where necessary to prevent such warnings.
As the original patch this checkpatch warning is ignored:
"WARNING: Adding new packed members is to be done with care"Cc: Masahiro Yamada
Cc: Tom Rini
Signed-off-by: Jeroen Hofstee
Acked-by: Masahiro Yamada -
Now MIN, MAX, MIN3, MAX are not used.
Going forward, use min, max, min3, max3.Signed-off-by: Masahiro Yamada
-
Since clang has a different definition for uninitialized_var
it will complain that it is redefined in include/compiler.h.
Since these are already defined in linux/compiler.h just remove
this instance.Cc: Masahiro Yamada
Cc: Tom Rini
Signed-off-by: Jeroen Hofstee -
The section name and the C variable name seem to be opposite.
Signed-off-by: Masahiro Yamada
Cc: Marek Vasut
Acked-by: Marek Vasut -
Now config_cmd_defaults.h is empty so it can be deleted safely.
Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass -
Since CONFIG_CMD_IMPORTENV is defined in config_cmd_defaults.h,
it should be enabled for all the boards except bf506f-ezkit
that undefs it explicitely.Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
Tested-by: Simon Glass -
Since CONFIG_CMD_GO is defined in config_cmd_defaults.h
(and no board undefs it its own header), it can be moved to
Kconfig with the default value "y".Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
Tested-by: Simon Glass -
Since CONFIG_CMD_EXPORTENV is defined in config_cmd_defaults.h,
it should be enabled for all the boards except bf506f-ezkit
that undefs it explicitely.Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
Tested-by: Simon Glass -
Since CONFIG_CMD_CRC32 is defined in config_cmd_defaults.h,
it is enabled for all the boards except the ones undefining it
explicitly:
kwb
tseries_mmc
tseries_nand
tseries_spi
vct_platinum_onenand_small
vct_platinum_small
vct_platinumavc_onenand_small
vct_platinumavc_small
vct_premium_onenand_small
vct_premium_smallThe default value of this config option should be "y" and
"# CONFIG_CMD_CRC32 is not set" should be added for those exceptions.Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass -
CONFIG_CMD_BOOTM is defined in config_cmd_defaults.h
which is forcebly included from each board.
So, the default value of "config CMD_BOOTM" should be "y".For some boards undefining it (bf506f-ezkit, controlcenterd_TRAILBLA,
controlcenterd_TRAILBLAZER_DEVELOP, controlcenterd_TRAILBLAZER),
"# CONFIG_CMD_BOOTM is not set" should be added to their defconfig.Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass -
If this option is enabled, the objects under lib/ directory
are compiled with speed optimization, not size optimization.
(Currently, only used by some Blackfin boards.)Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
Tested-by: Simon Glass -
Scsi disks need to be probed before we try to access them, otherwise all
accesses fail with: ** Bad device size - scsi 0 **.Reported-by: Karsten Merker
Signed-off-by: Hans de Goede
Reviewed-by: Stephen Warren
Tested-by: Karsten Merker -
- add support for 'fastboot flash' command for eMMC devices
Signed-off-by: Steve Rae
