07 Jun, 2014
21 commits
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Enable support of nand ecclayout command.
Acked-By: Murali Karicheri
Acked-by: Vitaly Andrianov
Signed-off-by: WingMan Kwok
Signed-off-by: Ivan Khoronzhuk -
Currently PWREMU_MGMT is not configured in the Linux generic UART
driver as this register seems to be specific TI UART IP. So this
needs to be enabled in u-boot to use UART1 from kernel space.Acked-By: Vitaly Andrianov
Signed-off-by: Murali Karicheri
Signed-off-by: Ivan Khoronzhuk -
With the changes to the i2c framework (and adopting the omap24xx_i2c
driver to them) we can no longer call i2c functions prior to gd having
been set and cleared. When SPL booting, this is handled by setting gd
to point to SRAM in s_init. However in the cases where we are loaded
directly by ROM (memory mapped NOR or QSPI) we need to make use of the
normal hooks to slightly delay these calls.Signed-off-by: Tom Rini
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We have two contexts for booting these platforms. One is SPL which is
roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main,
board_init_f from SPL, ... then U-Boot loads. The other is a
memory-mapped XIP case (NOR or QSPI) where we do not run an SPL. In
this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init,
_main, regular board_init_f.In the first case s_init will set a valid gd and then be able to call
sdram_init which in many cases will need i2c (which needs a valid gd for
gd->cur_i2c_bus). In this second case we must (and are able to and
should) defer sdram_init() into dram_init() called by board_init_f as gd
will have been set in _main and cleared in board_init_f.Signed-off-by: Tom Rini
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The patch populates the slave data which will be used by flash driver to
set the flash quad enable bit.Signed-off-by: Sourav Poddar
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The ePOS EVM and EVM SK have QSPI as an option to boot. Add a qspiboot
target that utilizes QSPI for env and so forth as an example of best
practices. As QSPI is booted from directly we need to chang
CONFIG_SYS_TEXT_BASE.Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices
we need to handle that elsewhere, once NAND support is also added.Signed-off-by: Sourav Poddar
Signed-off-by: Tom Rini -
updates documentation with explanation on how to select ECC schemes.
Signed-off-by: Pekon Gupta
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This patch add support for BCH16_ECC to omap_gpmc driver.
*need to BCH16 ECC scheme*
With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes
Flash devices have become more suspectible to bit-flips. Thus stronger
ECC schemes are required for protecting the data.
But stronger ECC schemes have come with larger-sized ECC syndromes which require
more space in OOB/Spare. This puts constrains like;
(a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
(b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy following equation:
OOBsize per page >= 26 * (page-size / 512)Signed-off-by: Pekon Gupta
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GPMC can support simultaneous processing of 8 512Byte data chunks, in parallel
Signed-off-by: Pekon Gupta
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OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros
to configure GPMC controller for x7 or x8 bit device connected to its interface.
Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above
macros can be completely removed.Signed-off-by: Pekon Gupta
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GPMC controller needs to be configured based on bus-width of the NAND device
connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI
parameters is not possible in following situations:
SPL: SPL NAND drivers does not support ONFI parameter reading.
U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init()
which is called before probing for devices, hence any ONFI parameter
information is not available during GPMC initialization.Thus, OMAP NAND driver expected board developers to explicitely write GPMC
configurations specific to NAND device attached on board in board files itself.
But this was troublesome for board manufacturers as they need to dive into
lengthy platform & SoC documents to find details of GPMC registers and
appropriate configurations to get NAND device working.This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config
hich indicates that connected NAND device has x16 bus-width. And then based on
this config GPMC driver itself initializes itself based on NAND bus-width. This
keeps board developers free from knowing GPMC controller specific internals.Signed-off-by: Pekon Gupta
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As per following Sections in ONFI Spec, GET_FEATURES and SET_FEATURES also need
byte-addressing on 16-bit devices.*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
data bus. The host shall not issue commands that use a word data width on x16
devices until the host determines the device supports a 16-bit data bus width
in the parameter page."*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
16-bit width. All address and command line transfers shall use only the lower
8-bits of the data bus. During command transfers, the host may place any value
on the upper 8-bits of the data bus. During address transfers, the host shall
set the upper 8-bits of the data bus to 00h."So porting following commit from linux kernel
commit e34fcb07a6d57411de6e15a47724fbe92c5caa42
Author: David Mosberger (preserving authorship)
mtd: nand: fix GET/SET_FEATURES address on 16-bit devicesSigned-off-by: Pekon Gupta
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As per following Sections in ONFI Spec, NAND_CMD_READID should use only
lower 8-bit for transfering command, address and data even on x16 NAND device.*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
data bus. The host shall not issue commands that use a word data width on x16
devices until the host determines the device supports a 16-bit data bus width
in the parameter page."*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
16-bit width. All address and command line transfers shall use only the lower
8-bits of the data bus. During command transfers, the host may place any value
on the upper 8-bits of the data bus. During address transfers, the host shall
set the upper 8-bits of the data bus to 00h."Thus porting following commit from linux-kernel to ensure that column address
is not altered to align to x16 bus when issuing NAND_CMD_READID command.commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7
mtd: nand: force NAND_CMD_READID onto 8-bit bus
Author: Brian Norris (preserving authorship)The NAND command helpers tend to automatically shift the column address
for x16 bus devices, since most commands expect a word address, not a
byte address. The Read ID command, however, expects an 8-bit address
(i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
0x20).This fixes the column address for a few drivers which imitate the
nand_base defaults.Signed-off-by: Pekon Gupta
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Porting below commit from linux-tree, preserving original authorship & commit log
commit bd9c6e99b58255b9de1982711ac9487c9a2f18be
Author: Brian Norris
mtd: nand: don't use read_buf for 8-bit ONFI transfersUse a repeated read_byte() instead of read_buf(), since for x16 buswidth
devices, we need to avoid the upper I/O[16:9] bits. See the following
commit for reference:commit 05f7835975dad6b3b517f9e23415985e648fb875 (from linux-tree)
Author: Uwe Kleine-König
Date: Thu Dec 5 22:22:04 2013 +0100mtd: nand: don't use {read,write}_buf for 8-bit transfers
Now, I think that all barriers to probing ONFI on x16 devices are
removed, so remove the check from nand_flash_detect_onfi().Signed-off-by: Pekon Gupta
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This patch
omap-elm.c: replaces -ve integer value returned during errorneous condition,
with proper error-codes.
omap-gpmc.c: updates omap-gpmc driver to pass error-codes returned from
omap-elm driver to upper layersSigned-off-by: Pekon Gupta
Reviewed-by: Stefan Roese -
This patch tries to avoid some local pointer dereferences, by using common
local variables in omap_correct_data_bch()Signed-off-by: Pekon Gupta
Reviewed-by: Stefan Roese -
This patch renames 'struct nand_bch_priv' which currently holds private data only
for BCH ECC schemes, into 'struct omap_nand_info' so that same can be used for
all ECC schemesSigned-off-by: Pekon Gupta
Reviewed-by: Stefan Roese -
This patch prepares to refactor 'struct nand_bch_priv' -> 'struct omap_nand_info'
And thus performs following clean-ups:
- remove nand_bch_priv.type: use nand_bch_priv.ecc_scheme instead
- remove nand_bch_priv.mode:Signed-off-by: Pekon Gupta
Reviewed-by: Stefan Roese -
This patch adds macros for following parameters of ELM Hardware engine
- ELM_MAX_CHANNELS: ELM can process 8 data streams simultaneously
- ELM_MAX_ERRORS: ELM can detect upto 16 ECC error when using BCH16 schemeSigned-off-by: Pekon Gupta
Reviewed-by: Stefan Roese -
ELM hardware engine support ECC error detection for multiple ECC strengths like
+------+------------------------+
|Type | ECC syndrome length |
+------+------------------------+
|BCH4 | 6.5 bytes = 13 nibbles |
|BCH8 | 13 byte = 26 nibbles |
|BCH16 | 26 bytes = 52 nibbles |
+------+------------------------+Current implementation of omap_elm driver uses ECC syndrom length (in 'nibbles')
to differentiate between BCH4/BCH8/BCH16. This patch replaces it with 'bch_type'Signed-off-by: Pekon Gupta
Reviewed-by: Stefan Roese -
There is no dependency of omap_elm.c on omap_gpmc.h
Signed-off-by: Pekon Gupta
Reviewed-by: Stefan Roese
02 Jun, 2014
1 commit
31 May, 2014
1 commit
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Setting ps_hold ought to be one of the first things we do when we
first boot up. If we wait until the main u-boot runs we won't set it
in time and the PMIC may power us back off.Signed-off-by: Doug Anderson
Signed-off-by: Akshay Saraswat
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang
29 May, 2014
1 commit
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Add CONFIG_SYS_GENERIC_BOARD for all Exynos4 boards.
Signed-off-by: Piotr Wilczek
Cc: Przemyslaw Marczak
Cc: Lukasz Majewski
Signed-off-by: Minkyu Kang
28 May, 2014
12 commits
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Add the ability to display the code offset of an initcall even after it
is relocated. This makes it much easier to relate initcalls back to the
U-Boot System.map file.Signed-off-by: Simon Glass
Signed-off-by: Minkyu Kang -
The backlight uses FETs on the TPS65090. Enable this so that the display
is visible.Signed-off-by: Simon Glass
Reviewed-by: Lukasz Majewski
Signed-off-by: Minkyu Kang -
Enable LCD for snow. This is a 1366 x 768 panel.
Signed-off-by: Simon Glass
Signed-off-by: Minkyu Kang -
There is quite a tight deadline in enabling PSHOLD, less than a second.
In some cases (e.g. with USB download), U-Boot takes longer than that
to load, so the board powers off before U-Boot starts.Add a call in SPL to enable PSHOLD.
Signed-off-by: Simon Glass
Reviewed-by: Lukasz Majewski
Signed-off-by: Minkyu Kang -
The TSP65090 is a PMIC on some exynos5 boards. The init function is
called for the TPS65090 pmic. If that device is not a part of the device
tree (returns -ENODEV) then continue. Otherwise return a failure.Signed-off-by: Aaron Durbin
Signed-off-by: Simon Glass
Reviewed-by: Simon Glass
Signed-off-by: Minkyu Kang -
The current pmic i2c code assumes the current i2c bus is
the same as the pmic device's bus. There is nothing ensuring
that to be true. Therefore, select the proper bus before performing
a transaction.Signed-off-by: Aaron Durbin
Signed-off-by: Simon Glass
Acked-by: Heiko Schocher
Reviewed-by: Simon Glass
Signed-off-by: Minkyu Kang -
The TPS65090 pmic chip can be on exynos5250 boards. Therefore,
select the appropriate config option for TPS65090 devices.This commit should really use exynos5-dt.c, when it is available.
Signed-off-by: Simon Glass
Reviewed-by: Simon Glass
Signed-off-by: Minkyu Kang -
This adds driver support for the TPS65090 PMU. Support includes
hooking into the pmic infrastructure so that the pmic commands
can be used on the console. The TPS65090 supports the following
functionality:- fet enable/disable/querying
- getting and setting of charge stateEven though it is connected to the pmic infrastructure it does
not hook into the pmic charging charging infrastructure.The device tree binding is from Linux, but only a small subset of
functionality is supported.Signed-off-by: Tom Wai-Hong Tam
Signed-off-by: Hatim Ali
Signed-off-by: Katie Roberts-Hoffman
Signed-off-by: Rong Chang
Signed-off-by: Sean Paul
Signed-off-by: Vincent Palatin
Signed-off-by: Aaron Durbin
Signed-off-by: Simon Glass
Signed-off-by: Minkyu Kang -
This enum should be common across all PMICs rather than having it
independently defined with the same name in multiple places.Signed-off-by: Simon Glass
Signed-off-by: Minkyu Kang -
Commit be3b51aa did this mostly, but several have been added since. Do the
job again.Signed-off-by: Simon Glass
Acked-by: Lukasz Majewski
Signed-off-by: Minkyu Kang -
This is not used by any boards now. Drop it to avoid confusion.
Signed-off-by: Simon Glass
Signed-off-by: Minkyu Kang -
Now that the GPIO numbering series has been applied, we can use the correct
GPIO for the EC interrupt.Signed-off-by: Simon Glass
Signed-off-by: Minkyu Kang
27 May, 2014
4 commits
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In this configuration the environment will save in file: uboot.env of
mmc card.Signed-off-by: Josh Wu
Signed-off-by: Andreas Bießmann -
Also we enable the mmc command in configuration file.
As both CONFIG_CMD_MMC and CONFIG_CMD_USB use the CONFIG_DOS_PARTITION,
so remove the redundant CONFIG_DOS_PARTITION definition.Signed-off-by: Josh Wu
Signed-off-by: Andreas Bießmann -
As at91 board config file will include the SoC header, so we can remove
the ARM926EJS definition in board config files.Signed-off-by: Josh Wu
Signed-off-by: Andreas Bießmann -
Now the AT91FAMILY is already defined in the at91 SoC header. The at91
board config file will include the SoC header file.So we can remove the redundant AT91FAMILY definition in at91 board
config files.Signed-off-by: Josh Wu
[rebase patch]
Signed-off-by: Andreas Bießmann
