07 Oct, 2014
1 commit
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Fix a trivial conflict in dw_mmc.c after talking with Marek.
Conflicts:
drivers/mmc/dw_mmc.cSigned-off-by: Tom Rini
06 Oct, 2014
2 commits
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Make the SoCFPGA MMC stub pick clock via the clock manager
frequency accessors instead of hard-coding the frequency.Also fix calloc() misuse.
Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Dinh Nguyen -
The dw_mmc driver was responding to errors with debug(). Change that
to prinf()/puts() respectively so that any errors are immediately
obvious. Also adjust english in comments.Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Cc: Pantelis Antoniou
Acked-by: Chin Liang See
03 Oct, 2014
6 commits
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dw_mmc driver was responding to errors with debug(). Change that to
prinf so that any errors are immediately obvious. Also adjust english
in comments.Signed-off-by: Pavel Machek
Acked-by: Pantelis Antoniou -
After setting the bus width, the extended CSD register is read. Some selected
fields are compared with previously read extended CSD register fields. In this
comparison the EXT_CSD_ERASE_GROUP_DEF field is compared. But this field is
previously written under certain circumstances. And then the comparison fails.Only compare read-only fields. Therefore compare field EXT_CSD_HC_WP_GRP_SIZE
instead of field EXT_CSD_ERASE_GROUP_DEF.Signed-off-by: Mario Schuknecht
Acked-by: Pantelis Antoniou -
In function mvebu_mmc_write notice command timeout. It is possible that a
command is done, but a timeout occurred.Enable timeout in set bus function.
Set window registers. Without that I could not use the driver on a Kirkwood
88F6282 SoC.Set high capacity and 52MHz driver feature.
Signed-off-by: Mario Schuknecht
Reviewed-by: Stefan Roese
Acked-by: Pantelis Antoniou -
The capacity and lba for an MMC device with part_num 0 reflects the
whole device. When mmc_switch_part() successfully switches to a
partition, the capacity is changed to that partition. As partition 0
does not physically exist, attempts to switch back to the whole device
will indicate an error, but the capacity setting for the whole device
must still be restored to match the partition.Signed-off-by: Peter A. Bigot
Tested-by: Tom Rini
Acked-by: Pantelis Antoniou -
if we set manually this bit on the eMMC card using mmc_switch(...),
we also have to set it within our (before read) internal structure
'ext_csd'.Otherwise following checks on this will fail.
Acked-by: Pantelis Antoniou
Signed-off-by: Hannes Petermaier -
Wait data transfer till the data end bit other than the data block end
bit is set.Acked-by: Pantelis Antoniou
Signed-off-by: Sonic Zhang
25 Sep, 2014
2 commits
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The macro MIN, MAX is defined as the aliase of min, max,
respectively.Signed-off-by: Masahiro Yamada
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This would be useful to start moving various config options.
Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
Tested-by: Simon Glass
09 Sep, 2014
1 commit
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For LS1, esdhc is big-endian IP. Accessing the registers
should be in big-endian mode. So we use esdhc_read32()
to read Host controller capabilities register for LS1.For LS1, when using CMD12, cmdtype need to be set to
ABORT, otherwise, next read command will hang.Signed-off-by: Alison Wang
30 Aug, 2014
2 commits
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Cleanups as suggested by wd on mailing list.
Signed-off-by: Pavel Machek
Acked-by: Chin Liang See -
Structure defining clock manager hardware was wrong, leading to
wrong registers being accessed and hang in MMC init.This fixes structure to match hardware.
Signed-off-by: Pavel Machek
02 Aug, 2014
4 commits
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If the MCI IP version >= 0x300, it supports hight speed mode
option, this patch enable it.Signed-off-by: Bo Shen
Acked-by: Pantelis Antoniou -
The mode register is different between MCI IP version.
So, according to MCI IP version to set the mode register.Signed-off-by: Bo Shen
Acked-by: Pantelis Antoniou -
To fix the clock divider calculation error when the controller
clock same as the operating frequency. This is known as bypass
mode. In this mode, the divider should be 0.Signed-off-by: Chin Liang See
Cc: Pantelis Antoniou
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Mischa Jonker -
Implement SD driver for the S3C24xx family. This implementation
is currently only capable of using the PIO transfers, DMA is not
supported.Signed-off-by: Marek Vasut
Cc: Kyungmin Park
Cc: Lukasz Majewski
Cc: Minkyu Kang
Cc: Pantelis Antoniou
Cc: Vladimir Zapolskiy
Acked-by: Pantelis Antoniou
01 Aug, 2014
2 commits
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Seems like the controller doesn't support the flag. None of the hi-speed cards
I've tried could be read, while they successfully worked with the quirk enabled.Signed-off-by: Lubomir Rintel
Tested-by: Stephen Warren -
This patch add Marvell kirkwood MVSDIO/MMC driver
and enable it for Sheevaplugs and OpenRD boards.Signed-off-by: Gerald Kerma
Reviewed-by: Stefan Roese
Acked-by: Pantelis Antoniou
28 Jul, 2014
1 commit
19 Jul, 2014
2 commits
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Add missing prototypes for global functions and
make local functions static.cc: panto@antoniou-consulting.com
Signed-off-by: Jeroen Hofstee -
use weak instead of alias to prevent some clang warnings.
Signed-off-by: Jeroen Hofstee
07 Jul, 2014
1 commit
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The DMA code in sunxi_mmc.c is broken. mmc_trans_data_by_dma() allocates the
dma descriptors on the stack, and then exits while the dma transfer is in
progress, so the dma engine is reading stack memory which at that point may
be re-used. So far we've gotten away with this by luck, but recent u-boot
changes have shifted the stack start address by 16 bytes, which combined
with dma alignment now exposes this problem.Since we end up just busy waiting for the dma engine anyway, this commit
fixes things by simply removing the dma code, resulting in smaller bug-free
code.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell
19 Jun, 2014
1 commit
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commit 18b06652cd "tools: include u-boot version of sha256.h"
unconditionally forced the sha256.h from u-boot to be used
for tools instead of the host version. This is fragile though
as it will also include the host version. Therefore move it
to include/u-boot to join u-boot/md5.h etc which were renamed
for the same reason.cc: Simon Glass
Signed-off-by: Jeroen Hofstee
12 Jun, 2014
2 commits
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Cleanup to balance malloc/free calls.
Signed-off-by: Darwin Rambo
Reviewed-by: Steve Rae
Acked-by: Pantelis Antoniou -
Rather than just returning -1 everywhere, try to return something
meaningful from mmc_select_hwpart(). Note that most other MMC functions
don't do this, including functions called from mmc_select_hwpart(), so
I'm not sure how effective this will be. Still, it's one less place with
hard-coded -1.Suggested-by: Pantelis Antoniou
Signed-off-by: Stephen Warren
Acked-by: Pantelis Antoniou
02 Jun, 2014
1 commit
27 May, 2014
1 commit
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Signed-off-by: Josh Wu
[fix checkpatch line length warning]
Signed-off-by: Andreas Bießmann
25 May, 2014
1 commit
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On Mon, 2014-05-05 at 14:18 +0200, Stefan Roese wrote:
> > + case 1:
> > +#if CONFIG_MMC1_PG> Are you sure that this is correct and shouldn't be:
>
> +#ifdef CONFIG_MMC1_PG
>
> ?It's "correct" in so far as it works (the boards.cfg config stuff
#defines things to 1), but I think you are right that it isn't the
preferred style. But...> A quick scan through this patch series shows that this define
> is not set at all. Perhaps its outdated? Or is it used to support
> some other sunxi SoC? Not sure, perhaps it should be removed for
> now....I had thought that it was to support some other board which wasn't
being upstreamed right now, so eventually useful and harmless for now,
but I've just checked and it isn't actually used by any of the boards in
u-boot-sunxi.git. So rather than fix it to use #ifdef lets drop it.
Rather than resend the entire series, here is v5.1 of this patch.> Other than this please add my:
>
> Reviewed-by: Stefan RoeseThanks!
8From 20704e35a41664de5f516ed0e02981ac06085102 Mon Sep 17 00:00:00 2001
From: Ian Campbell
Date: Fri, 7 Mar 2014 04:29:39 +0000
Subject: [PATCH v5.1 7/8] sunxi: mmc supportThis adds support for the MMC controller on the Allwinner A20 (sun7i)
processor.Signed-off-by: Henrik Nordstrom
Signed-off-by: Luke Leighton
Signed-off-by: Oliver Schinagl
Signed-off-by: Wills Wang
Signed-off-by: Ian Campbell
Reviewed-by: Marek Vasut
Reviewed-by: Stefan Roese
Cc: Tom Cubie
Cc: Aaron Maoye
Cc: Pantelis Antoniou
Reviewed-by: Tom Rini
23 May, 2014
6 commits
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In 7168977 we made calls to check_and_invalidate_dcache_range()
conditional on !CONFIG_SYS_FSL_ESDHC_USE_PIO. Only define this function
in this case as well.Signed-off-by: Tom Rini
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This enables specifying which eMMC HW partition to target for any U-Boot
command that uses the generic get_partition() function to parse its
command-line arguments.Acked-by: Pantelis Antoniou
Signed-off-by: Stephen Warren -
This patch adds functions for read, write and authentication
key programming for the Replay Protected Memory Block partition
in the eMMC.Acked-by: Pantelis Antoniou
Signed-off-by: Pierre Aubert -
MMC switch command for unsupported feature (e.g. bus width) sets a switch
error bit in card status. This bit should be checked, and, if it's set,
no access with new controller settings should be performed.Acked-by: Pantelis Antoniou
Signed-off-by: Andrew Gabbasov -
mmc_init() doesn't call get_timer() anymore if MMC is already
initialized.Minor formatting fix.
Acked-by: Pantelis Antoniou
Signed-off-by: Mateusz Zalega
22 May, 2014
1 commit
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When configure the fsl_esdhc driver to PIO mode by defining
"CONFIG_SYS_FSL_ESDHC_USE_PIO", the SD/MMC read and write will fail.Two bugs in the driver to cause the issue:
1. The read buffer was invalidated after reading from DATAPORT register,
which should be only applied to DMA mode. The valid data in cache was
overwritten by physical memory.
2. The watermarks are not set in PIO mode, will cause according state not
be set.Acked-by: Pantelis Antoniou
Signed-off-by: Ye.Li
20 May, 2014
1 commit
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Conflicts:
boards.cfgConflicts were trivial once u-boot-arm/master boards.cfg was
reformatted (commit 6130c146) to match u-boot/master's own
reformatting (commit 1b37fa83).
16 May, 2014
2 commits
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To reuse the code, added the s5p_sdhci_core_init function.
Before applied this patch, didn't use the 8-bit mode at exynos baord.
Because it didn't set "MMC_MODE_8BIT".Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
Signed-off-by: Minkyu Kang -
Set the ddr mode capability by default.
Signed-off-by: Jaehoon Chung
Tested-by: Lukasz Majewski
Acked-by: Lukasz Majewski
Signed-off-by: Minkyu Kang
