Eric Lee / smarc-uboot

30 Sep, 2011

1 commit

  • e46fedfeb   powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros ... Browse Code »

    Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW
    macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS.
    This is necessary for the assembly-language code that relocates CCSR, since
    the assembler does not understand 64-bit constants.

    CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the
    CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it
    should not be defined in a board header file. Similarly,
    CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so
    it should also not be defined in the board header file.

    CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that
    CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT,
    and so CCSR will not be relocated.

    Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot
    builds (e.g. NAND) are required to relocate CCSR only during the last stage
    (i.e. the "real" U-Boot). All other stages should define
    CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated.

    README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros.

    Signed-off-by: Timur Tabi
    Signed-off-by: Kumar Gala

    Timur Tabi
     

16 Jul, 2010

1 commit

  • f51cdaf19   83xx/85xx/86xx: LBC register cleanup ... Browse Code »

    Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
    dedicated to defining and manipulating the LBC registers. Merge
    this into a single spot.

    To do this, we have to decide on a common name for the data structure
    that holds the lbc registers - it will now be known as fsl_lbc_t, and we
    adopt a common name for the immap layouts that include the lbc - this was
    previously known as either im_lbc or lbus; use the former.

    In addition, create accessors for the BR/OR regs that use in/out_be32
    and use those instead of the mismash of access methods currently in play.

    I have done a successful ppc build all and tested a board or two from
    each processor family.

    Signed-off-by: Becky Bruce
    Acked-by: Kim Phillips
    Signed-off-by: Kumar Gala

    Becky Bruce
     

11 Jun, 2008

2 commits

14 Aug, 2007

1 commit

  • 61a21e980   85xx start.S cleanup and exception support ... Browse Code »

    From: Ed Swarthout

    Support external interrupts from platform to eliminate system hangs.
    Define CONFIG_INTERRUPTS board configure option to enable.
    Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.

    Remove extra cpu initialization redundant with hardware initialization.
    Whitespace cleanup.

    Define and use _START_OFFSET consistent with other processors using
    ppc_asm.tmpl

    Move additional code from .text to boot page to make room for
    exception vectors at start of image.

    Handle Machine Check, External and Critical exceptions.

    Fix e500 machine check error determination in traps.c

    TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.

    Signed-off-by: Ed Swarthout
    Acked-by: Andy Fleming

    Andy Fleming
     

22 Jun, 2007

1 commit

13 Mar, 2006

1 commit

10 Jul, 2004

1 commit

16 Oct, 2003

1 commit