10 May, 2014

2 commits


09 May, 2014

1 commit


26 Apr, 2014

2 commits


24 Apr, 2014

2 commits


23 Apr, 2014

14 commits

  • Add support of 2 stage NAND/SD boot loader using SPL framework.
    PBL initialise the internal SRAM and copy SPL, this further
    initialise DDR using SPD and environment and copy u-boot from
    NAND/SD to DDR, finally SPL transfer control to u-boot.
    NOR uses CS1 instead of CS2 when NAND boot, fix it.

    Signed-off-by: Shaohui Xie
    Reviewed-by: York Sun

    Shaohui Xie
     
  • Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
    PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
    SPL further initializes DDR using SPD and environment and copy
    u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control
    to u-boot.

    Signed-off-by: Shengzhou Liu
    Reviewed-by: York Sun

    Shengzhou Liu
     
  • Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
    PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
    SPL further initializes DDR using SPD and environment and copy
    u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers
    control to u-boot.

    Signed-off-by: Shengzhou Liu
    [York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH]
    Reviewed-by: York Sun

    Shengzhou Liu
     
  • Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
    here, PBL initialise the internal SRAM and copy SPL(160KB). This further
    initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
    Finally SPL transer control to u-boot.

    Initialise/create followings required for SPL framework
    - Add spl.c which defines board_init_f, board_init_r
    - update tlb and ddr accordingly

    Signed-off-by: Prabhakar Kushwaha
    Reviewed-by: York Sun

    Prabhakar Kushwaha
     
  • Add support of 2 stage NAND boot loader using SPL framework.
    here, PBL initialise the internal SRAM and copy SPL(160KB). This further
    initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
    Finally SPL transer control to u-boot.

    Initialise/create followings required for SPL framework
    - Add spl.c which defines board_init_f, board_init_r
    - update tlb and ddr accordingly

    Signed-off-by: Prabhakar Kushwaha
    Reviewed-by: York Sun

    Prabhakar Kushwaha
     
  • T1040RDB, T1042RDB header files are very similar so merged into new header file T104xRDB.
    T104xRDB header file can support both T1040RDB and T1042RDB_PI header.

    Patch makes following changes
    -Update Boards.cfg file for T1040RDB and T1042RDB_PI
    -Add new T104xRDB header file
    -Delete T1040RDB, T1042RDB_PI header file

    Signed-off-by: Vijay Rai
    Signed-off-by: Priyanka Jain
    Reviewed-by: York Sun

    vijay rai
     
  • T1040QDS_D4 is a variant of T1040QDS, with additional circuit to support
    DDR4 memory. Tested with MTA9ASF51272AZ-2G1AYESZG.

    Signed-off-by: York Sun

    York Sun
     
  • Secure Boot Target is added for T1040QDS and T1040RDB
    Changes:
    For Secure boot, CPC is configured as SRAM and used as house
    keeping area which needs to be disabled.
    So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and
    CONFIG_T1040RDB

    Signed-off-by: Gaurav Rana
    Signed-off-by: Aneesh Bansal
    Reviewed-by: York Sun

    Aneesh Bansal
     
  • Secure Boot Target is added for T2080QDS
    Changes:
    For Secure boot, CPC is configured as SRAM and used as house
    keeping area which needs to be disabled.
    So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS.

    Signed-off-by: Aneesh Bansal
    Reviewed-by: York Sun

    Aneesh Bansal
     
  • Secure Boot Target is added for T4240QDS and T4160QDS
    Changes:
    For Secure boot, CPC is configured as SRAM and used as house
    keeping area which needs to be disabled.
    So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS.

    Signed-off-by: Aneesh Bansal
    Reviewed-by: York Sun

    Aneesh Bansal
     
  • Changes:
    1. L2 cache is being invalidated by Boot ROM code for e6500 core.
    So removing the invalidation from start.S
    2. Clear the LAW and corresponding configuration for CPC. Boot ROM
    code uses it as hosekeeping area.
    3. For Secure boot, CPC is configured as SRAM and used as house
    keeping area. This configuration is to be disabled once in uboot.
    Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
    As a result cache invalidation function was getting skipped in
    case CPC is configured as SRAM.This was causing random crashes.

    Signed-off-by: Ruchika Gupta
    Signed-off-by: Aneesh Bansal
    Reviewed-by: York Sun

    Aneesh Bansal
     
  • In case of secure boot from NAND, the DDR is initialized by the
    BootROM using the config words (CF_WORDS) in the CF_HEADER
    and u-boot image is copied from NAND to DDR by the BootROM.
    So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND

    Signed-off-by: Aneesh Bansal
    Reviewed-by: York Sun

    Aneesh Bansal
     
  • Add NOR, SPI and SD secure boot targets for BSC9132QDS.

    Changes:
    - Debug TLB entry is not required for Secure Boot Target.

    Signed-off-by: Aneesh Bansal
    Reviewed-by: York Sun

    Aneesh Bansal
     
  • For KVM we have a special PV machine type called "ppce500". This machine
    is inspired by the MPC8544DS board, but implements a lot less features
    than that one.

    It also provides more PCI slots and is supposed to be enumerated by
    device tree only.

    This patch adds support for the generic ppce500 machine and tries to
    rely solely on device tree for device enumeration.

    Signed-off-by: Alexander Graf
    Acked-by: Scott Wood
    Reviewed-by: York Sun

    Alexander Graf
     

22 Apr, 2014

1 commit


20 Apr, 2014

1 commit


18 Apr, 2014

14 commits


17 Apr, 2014

1 commit


25 Mar, 2014

1 commit


14 Mar, 2014

1 commit