13 Mar, 2015
9 commits
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This patch enables the workaround for ARM errata 798870 for OMAP5 /
DRA7 which says "If back-to-back speculative cache line fills (fill
A and fill B) are issued from the L1 data cache of a CPU to the
L2 cache, the second request (fill B) is then cancelled, and the
second request would have detected a hazard against a recent write or
eviction (write B) to the same cache line as fill B then the L2 logic
might deadlock."An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced
here as well.Signed-off-by: Praveen Rao
Signed-off-by: Angela Stegmaier
Signed-off-by: Nishanth Menon
Tested-by: Matt Porter
Reviewed-by: Tom Rini -
omap_smc1 is now generic enough to remove duplicate
omap3_gp_romcode_call logic that omap3 introduced.As part of this change, move to using the generic lowlevel_init.S for
omap3 as well.Signed-off-by: Nishanth Menon
Tested-by: Matt Porter
Reviewed-by: Tom Rini -
This is in preperation of using generic cross OMAP code.
Signed-off-by: Nishanth Menon
Tested-by: Matt Porter
Reviewed-by: Tom Rini -
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors as well. The only
difference being the service being invoked for the function.So, convert the service to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add a
data barrier which is necessary as per recommendation.While at this, smc #0 is maintained as handcoded assembly thanks to
various gcc version eccentricities, discussion thread:
http://marc.info/?t=142542166800001&r=1&w=2Signed-off-by: Nishanth Menon
Tested-by: Matt Porter
Reviewed-by: Tom Rini -
621766: Under a specific set of conditions, executing a sequence of
NEON or vfp load instructions can cause processor deadlock
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set L1NEON to 1Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon
Tested-by: Matt Porter
Reviewed-by: Tom Rini -
430973: Stale prediction on replaced inter working branch causes
Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon
Tested-by: Matt Porter
Reviewed-by: Tom Rini -
454179: Stale prediction may inhibit target address misprediction on
next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE and disable branch size mispredict to 1Also provide a hook for SoC specific handling to take place if needed.
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon
Tested-by: Matt Porter
Reviewed-by: Tom Rini -
Add workaround for Cortex-A15 ARM erratum 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
will be widely different.Every SoC has slightly different manner of setting up access to L2ACLR
and similar registers since the Secure Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon
Tested-by: Matt Porter
Reviewed-by: Tom Rini -
The purpose of this build target is to do SPL over USB RNDIS. We remove
YMODEM, MMC and NAND (and re-set ENV to be built-in) as when those are needed
we can use the other build targets. This brings us well under size limit again.Signed-off-by: Tom Rini
11 Mar, 2015
1 commit
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Conflicts:
READMESigned-off-by: Tom Rini
10 Mar, 2015
13 commits
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Fix a typo in board/sunxi/Kconfig which caused VIDEO_LCD_PANEL_I2C to be
enabled on all sunxi boards. Also fix a compile error which shows up once
VIDEO_LCD_PANEL_I2C is actually disabled on most boards as it should be.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
This patch add support for Wexler TAB7200 tablet.
The Wexler TAB7200 is a A20 based tablet with 7 inch display(800x480),
capacitive touchscreen(5 fingers), 1G RAM, 4G NAND, micro SD card slot,
mini HDMI port, 3.5mm audio plug, 1 USB OTG port and 1 USB 2.0 port.Signed-off-by: Aleksei Mamlin
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
Use the AXP223 PMIC to detect VBUS for musb otg support.
Signed-off-by: Chen-Yu Tsai
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
This enables the musb glue layer to use the AXP221's VBUS detection
function to check for VBUS. This fixes otg support on the A23 q8h
tablets.Note that u-boot never calls musb_shutdown(), so once VBUS is enabled,
it is never disabled until the system is powered off, or the OS does
so. This can be used to our advantage to keep VBUS powered into the
OS, where support for AXP221 is not available yet.Fixes: 52defe8f6570 ("sunxi: musb: Check Vbus-det before enabling otg port power")
Signed-off-by: Chen-Yu Tsai
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
Some of the AXP PMICs support VBUS detection, i.e. checking whether
VBUS power input is available and usable (supplied by an external
source). A few boards use this instead of a separate GPIO to detect
VBUS on USB OTG.Signed-off-by: Chen-Yu Tsai
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
The Orange Pi Mini is an A20 based development board featuring 1G RAM, HDMI,
1Gbit ethernet, USB wifi, SATA, 2 sdcard slots (use the top one for booting),
2 USB 2.0 A receptacles, a micro USB B receptacle (otg) and a 3 ring 3.5 mm
jack connector for A/V.Also see: http://www.orangepi.org/
Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
The Orange Pi is an A20 based development board featuring 1G RAM, HDMI & VGA,
1Gbit ethernet, USB wifi, SATA, 4 USB 2.0 A receptacles, a micro USB B
receptacle (otg) and a 3 ring 3.5 mm jack connector for A/V.Also see: http://www.orangepi.org/
Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
The Wits Pro A20 DKT is an A20 Development KiT with 1G RAM, 4G NAND, sdio wifi,
1Gbit ethernet, 1024x768 lcd screen with ft5x_ts touchscreen and a ton of
IO connectors.Note there seem to be multiple sdcard slots on the board (4 in total), but
other then mmc0 none of these are hooked up by default, there is a ton of
dip-switches which likely allow hooking some of these up, but the documentation
of the board only describes the use of a fraction of them, so for now we
only support mmc0.Also see: http://www.merrii.com/en/pla_d.asp?id=163
Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
The Forfun Q88DB is an A13 tablet in the common Q8 format.
Features are 512MB RAM, 4GB NAND, 7" Display, RTL8188 Wifi, 2 cameras.
For more details see: http://linux-sunxi.org/Forfun_Q88DB
Signed-off-by: Jens Lucius
Acked-by: Ian Campbell
Signed-off-by: Ian Campbell -
The Mele I7 is a Allwinner based Android TV box.
It features a A31 SOC, 1G RAM, 8GB NAND, HDMI out, A/V out,
SPDIF, IrDA, 3 USB A, 1 USB micro OTG and Wireless LAN.Signed-off-by: Marcus Cooper
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
The MK808C is a Allwinner based Android TV dongle.
It features a A20 SOC, 1G RAM, 8GB NAND, HDMI out, A/V out,
1 USB A, 1 USB mini OTG, Bluetooth and Wireless LAN.Signed-off-by: Marcus Cooper
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
The Jesurun Q5 has a black plastic casing with the approximate dimensions of
100mm x 100mm x 24mm with rounded edges. In terms of hardware it features an
Allwinner A10 SoC with 1GB RAM and 8GB of NAND flash. The storage capacity can
be extended up to 32GB with a MicroSD card. The external connectors are: 2x
USB-A female supporting USB2.0, 3.5mm female jack for audio, HDMI female,
SPDIF, RJ45 LAN and Power. In addition the device has 1x red LED (hard wired to
power) and an programmable green led. On the board there is also an unpopulated
IR receiver and the UART. The devices is equipped with an AXP209 PMU.For more details see: http://linux-sunxi.org/Jesurun_Q5
Signed-off-by: Gábor Nyers
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
The tpr3 (timing skew) parameter is used in all supported versions of
the sunxi DRAM controller, but it was only enabled for sun4i in
47e3501a76894f4ba08bc61f33774bd5d39ff464.Signed-off-by: Adam Sampson
Acked-by: Siarhei Siamashka
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede
09 Mar, 2015
14 commits
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Added support to disable the start of application by using
a environment variable autostartSigned-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek -
While the Freescale ARMv8 board LS2085A will enter U-Boot both
on a master and a secondary (slave) CPU, this is not the common
behaviour on ARMv8 platforms. The norm is that U-Boot is entered
from the master CPU only, while the other CPUs are kept in
WFI (wait for interrupt) state.The code determining which CPU we are running on is using the
MPIDR register, but the definition of that register varies with
platform to some extent, and handling multi-cluster platforms
(such as the Juno) will become cumbersome. It is better to only
enable the multiple entry code on machines that actually need
it and disable it by default.Make the single entry default and add a special
ARMV8_MULTIENTRY KConfig option to be used by the
platforms that need multientry and set it for the LS2085A.
Delete all use of the CPU_RELEASE_ADDR from the Vexpress64
boards as it is just totally unused and misleading, and
make it conditional in the generic start.S code.This makes the Juno platform start U-Boot properly.
Signed-off-by: Linus Walleij
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This fixes a regression of e310b93ec1, affecting Ethernet on the Jetson
TK1, e.g.Signed-off-by: Jan Kiszka
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The way the PSCI DT update happens currently means we pull in
everywhere, including on ARMv8 and that in turn brings in
for some non-PSCI related things that header needs to deal
with.To fix this, we rework the hook slightly. A good portion of
arch/arm/cpu/armv7/virt-dt.c is common looking and I hope that when PSCI
is needed on ARMv8 we can re-use this by and large. So rename the
current hook to psci_update_dt(), move the prototype to and
add an #ifdef that will make re-use later easier.Reported-by: York Sun
Cc: Marc Zyngier
Cc: York Sun
Cc: Ian Campbell
Cc: Hans de Goede
Cc: Albert ARIBAUD
Signed-off-by: Tom Rini
Acked-by: York Sun -
The dfu mmc file buffer, which was static, now is allocated
by memalign(), so the malloc pool len should be also increased.Signed-off-by: Przemyslaw Marczak
Cc: Tom Warren -
The dfu mmc file buffer, which was static, now is allocated
by memalign(), so the malloc pool len should be also increased.Signed-off-by: Przemyslaw Marczak
Cc: Tom Rini -
The dfu mmc file buffer, which was static, now is allocated
by memalign(), so the malloc pool len should be also increased.Signed-off-by: Przemyslaw Marczak
Cc: Jagannadha Sutradharudu Teki
Cc: Michal Simek
Acked-by: Michal Simek -
Reduce the boot time of Odroid XU3 by disabling the memset
at malloc init.Signed-off-by: Przemyslaw Marczak
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Reduce the boot time of Odroid X2/U3 by disabling the memset
at malloc init.This was tested on Odroid X2.
A quick test with checking gpio pin state using the oscilloscope.
Boot time from start to bootcmd (change gpio state by memory write command):
- ~228ms - before this change (arch memset enabled for .bss clear)
- ~100ms - after this changeSigned-off-by: Przemyslaw Marczak
Reviewed-by: Simon Glass -
Reduce the boot time of Trats2 by disabling the memset
at malloc init.This was tested on Trats2.
A quick test with trace. Boot time from start to main_loop() entry:
- ~464ms - before this change (arch memset enabled for .bss clear)
- ~341ms - after this changeSigned-off-by: Przemyslaw Marczak
Reviewed-by: Simon Glass -
This commit introduces new config: CONFIG_SYS_MALLOC_CLEAR_ON_INIT.
This config is an expert option and is enabled by default.
The all amount of memory reserved for the malloc, is by default set
to zero in mem_malloc_init(). When the malloc reserved memory exceeds
few MiB, then the boot process can slow down.So disabling this config, is an expert option to reduce the boot time,
and can be disabled by Kconfig.Note:
After disable this option, only calloc() will return the pointer
to the zeroed memory area. Previously, without this option,
the memory pointed to untouched malloc memory region, was filled
with zeros. So it means, that code with malloc() calls should
be reexamined.Signed-off-by: Przemyslaw Marczak
Reviewed-by: Simon Glass -
For writing files, DFU implementation requires the file buffer
with the len at least of file size. For big files it requires
the same big buffer.Previously the file buffer was allocated as a static variable,
so it was a part of U-Boot .bss section. For 32MiB len of buffer
we have 32MiB of additional space, required for this section.The .bss needs to be cleared after the relocation.
This introduces an additional boot delay at every start, but usually
the dfu feature is not required at the standard boot, so the buffer
should be allocated only if required.This patch removes the static allocation of this buffer,
and alloc it with memalign after first call of function:
- dfu_fill_entity_mmc()
and the buffer is freed on dfu_free_entity() call.This was tested on Trats2.
A quick test with trace. Boot time from start to main_loop() entry:
- ~888ms - before this change (arch memset enabled for .bss clear)
- ~464ms - after this changeSigned-off-by: Przemyslaw Marczak
Reviewed-by: Simon Glass
Cc: Lukasz Majewski
Cc: Stephen Warren
Cc: Pantelis Antoniou
Cc: Tom Rini
Cc: Marek Vasut -
For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY,
will highly increase the memset/memcpy performance. This is able
thanks to the ARM multiple register instructions.Unfortunatelly the relocation is done without the cache enabled,
so it takes some time, but zeroing the BSS memory takes much more
longer, especially for the configs with big static buffers.A quick test confirms, that the boot time improvement after using
the arch memcpy for relocation has no significant meaning.
The same test confirms that enable the memset for zeroing BSS,
reduces the boot time.So this patch enables the arch memset for zeroing the BSS after
the relocation process. For ARM boards, this can be enabled
in board configs by defining: 'CONFIG_USE_ARCH_MEMSET'.This was tested on Trats2.
A quick test with trace. Boot time from start to main_loop() entry:
- ~1384ms - before this change
- ~888ms - after this changeSigned-off-by: Przemyslaw Marczak
Reviewed-by: Simon Glass
Cc: Albert Aribaud
Cc: Tom Rini -
This commit enables the following configs:
- CONFIG_USE_ARCH_MEMCPY
- CONFIG_USE_ARCH_MEMSET
This increases the performance of memcpy/memset
and also reduces the boot time.This was tested on Trats2.
A quick test with trace. Boot time from start to main_loop() entry:
- ~1527ms - before this change (arch memset enabled for .bss clear)
- ~1384ms - after this changeSigned-off-by: Przemyslaw Marczak
Reviewed-by: Simon Glass
Cc: Minkyu Kang
Cc: Akshay Saraswat
Cc: Simon Glass
Cc: Sjoerd Simons
08 Mar, 2015
1 commit
06 Mar, 2015
2 commits
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All the DM-related configuration options are described in Kconfig
helps. They should not be duplicated in README.Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass -
Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
