15 Mar, 2016
2 commits
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Q901 is PMOS, LCD_nPWREN should be at low voltage then output is 3V3.
If LCD_nPWREN is high, output is 2.4V which is not correct.Signed-off-by: Peng Fan
(cherry picked from commit b54bb7111af62a19a8aa930f8bbcf03f9515b863) -
Fix 74LV OE gpio index. pinmux is correct, but gpio index
is wrong, so gpio output will not have effect, since we
use wrong GPIO5_IO18, but not correct GPIO5_IO8.And at the end of the initialization of 74lv init, should
keep OE voltage level at LOW, but not high.Signed-off-by: Peng Fan
(cherry picked from commit be7654b4cd7edd456ca8d5df3a51cc04ee2fb8f4)
04 Mar, 2016
11 commits
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Some type style problems found by review-commits for previous patch
MLK-12483, fix them in this patch and re-check.Signed-off-by: Ye Li
(cherry picked from commit 8ada91778f7f28dd33b80f515a35d09c1398933c) -
Enable the configurations CONFIG_MODULE_FUSE and CONFIG_OF_SYSTEM_SETUP for
module fuse check. And modify board level codes for SD, FEC and EIM.Signed-off-by: Ye Li
(cherry picked from commit f9d57bc73807d14062721a793a2a55be69aa4973) -
To simplify kernel clock management, we switch to use DRAM_PLL for
DRAM controller and DDR PHY, but not use DRAM_ALT_CLK_ROOT.Signed-off-by: Peng Fan
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On i.MX7D TO1.1, design team adds a mux cell at the CKE path to fix the suspend
mode reset issue, but seems it add extra delay on CKE path, so CKE-CK timing violated.
When DDR enters self-refresh or retention for long time(> 15seconds per testing on some boards),
DDR data corruption occured, not able to decrease CKE delay, so we have to add extra
delay on all other signals to balance it.
DDR script needs to be fine-tuned according to this hardware change.For DDR3, since the timing margin is not good, we have to decrease the DDR frequency from
533Mhz to 400Mhz.Compass link:
http://compass.freescale.net/livelink/livelink?func=ll&objid=235010235&objAction=browse&sort=nameTest:
Overnight tests passed on all changed boards.Signed-off-by: Ye Li
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The BOOTCFG value used by bmode for SABRESD eMMC boot are actually for SD card.
Fixed the value to correct one.The issue was fixed in 2014.04 u-boot, but that patch seems missed during porting
to 2015.04.Signed-off-by: Ye Li
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Add mx6qarm2 new board revision support using mx6q pop SoC
Enable DRAM support for imx6q PoP SoC with populated LPDDR2
MT42L128M64D2DDR calibration script
http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/e5c6184940486bcbc28978d60ad3cd996c205a08
Test result: Stress test passed.Signed-off-by: Adrian Alonso
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Since i.MX7D SDB revB board has some HW changes, we have modify the BSP file to support new pinmux.
1. OTG2 PWR pin is changed to GPIO1_IO07.
2. A enet2_en pin is added for isolating enet2 signals with EPDC, we also add support for enet2.
3. pin6 of 74LV output is changed for CSI PWDN. Set output to high to power down it.This patch also tries to get the board id and apply changes according with it. Since current
RevB board does not burn GP1 fuse for board id, we have to check the TO rev instead even it is not very
exact. Will update this if any new way implemented.Signed-off-by: Ye.Li
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Current Micron DDR MT41K256M16HA-125 on i.MX6UL will be EOL. Plan is i.MX6UL
will use the new 20nm litho 4Gb DDR3L MT41K256M16TW-107.Update DDR script of mx6ul evk board for this new DDR, and use it as default.
http://compass.freescale.net/livelink/livelink?func=ll&objId=234910940&objAction=browse&viewType=1Test result:
Stress test passed.Meanwhile add build targets below for old DDR support:
mx6ul_14x14_evk_ddr_eol_android_defconfig
mx6ul_14x14_evk_ddr_eol_brillo_defconfig
mx6ul_14x14_evk_ddr_eol_defconfig
mx6ul_14x14_evk_ddr_eol_qspi1_defconfigSigned-off-by: Ye.Li
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i.MX7D TO1.1 changes DDR retension mode control to IOMUXC_GPR,
add support to this change for LPSR which needs to exit from
DDR retension mode.Signed-off-by: Anson Huang
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According to the Coverity result, a unsigned int variable is used fo less-
than-zero comparison, the result is never true. Need to fix the variable
type to signed int.Signed-off-by: Ye.Li
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ret should not use unsigned integer. Should use signed interger to
compare against 0.Signed-off-by: Peng Fan
09 Nov, 2015
1 commit
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http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4
http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1
arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI
arik_r2_sdb_ddr3_528_1.13.inc is for sabresd1.13
30 Oct, 2015
3 commits
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According to the latest datasheet(Rev. B, 07/2015), the VDD_SOC_IN
standby voltage should be 1.05V and on i.MX6QP, we can use the PMIC
'APS' mode in standby. we add a 25mV margin to cover the IR drop and
board tolerance, so the standby voltage of VDD_SOC_IN should be
setting to 1.075V.Signed-off-by: Bai Ping
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on i.MX6QP SDB board, the SW1A/B/C regulator is used by
VDD_SOC_IN, the regulator of VDD_ARM_IN is SW2, the voltage
setting for VDD_ARM_IN should be corresponding to SW2. So fix
the regulator mismatch issue on i.MX6QP SDB board.Signed-off-by: Bai Ping
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http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/963fbc75ef6d36e12819e81de23410749754e5ef
http://compass.freescale.net/livelink/livelink?func=ll&objId=234709279&objAction=browse&viewType=1Main change: (SDB board ddr density is different)
1. tRFC is different with density, tXS/tXPR refers tRFCTest Results:
2 MX6DP-SDB and 2 MX6QP-SDB boards passed overnight stress test.Signed-off-by: Peng Fan
23 Oct, 2015
1 commit
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ddr script update to 1.09:
http://compass.freescale.net/livelink/livelink?func=ll&objId=
234694528&objAction=browse&viewType=1arik_r2_sabre_ddr3_528_1.09.inc is for sabre-auto board.
arik_r2_sdb_ddr3_528_1.09.inc is for sabre-sd board.Changelog:
1. Optimize DQS duty cycle setting
2. Optimize ZQ PU/PD valueTest results:
2 ARD boards.
2 6QP-SDB boards.
1 6DP-SDB board.
All passed overnight memtester stress test.Signed-off-by: Peng Fan
(cherry picked from commit ba8dcef9d8e10e46130559ce6defe4411bd1d1a6)
13 Oct, 2015
1 commit
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According to the latest datasheet(Rev. C Draft 1, 10/2015) of
i.MX7D, change the VDD_SOC voltage to 0.95V in run mode, and
add a 25mV margin to cover the IR drop and board tolerance.
So setting VDD_SOC voltage to 0.975V.Signed-off-by: Bai Ping
10 Oct, 2015
1 commit
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IC team releases new DDR script "EVK_IMX6UL_DDR3L_400MHz_16bit_V1.2.inc",
update it to DCD and plugin for i.MX6UL 14x14 EVK board.Updated items:
Removed:
0x020c4084
0x021B0858
Value changed:
0x020E027C
0x020E0280
0x021B0008
0x021B000C
0x021B0010
0x021B0018
0x021B08C0The script versions of EVK board and Validation Board from the following link:
http://compass.freescale.net/livelink/livelink?func=ll&objId=234191407&obj
Action=browse&viewType=1Test Results:
Two boards passed overnight memtester stress test.Signed-off-by: Ye.Li
30 Sep, 2015
2 commits
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The PST bit can't be set too small which will cause performance drop.
Refer the commit for same issue on MX6UL 9x9 EVK, now fix it for 14x14 LPDDR2 ARM2
commit e1ca547d198dde94c4d8278c99499ec2d2008880Signed-off-by: Ye.Li
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The actual memory size is 256MB not 512MB, otherwise it has a wrap
problem in memory and will cause memtester failed.Signed-off-by: Ye.Li
24 Sep, 2015
1 commit
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enable bank interleave feature to improve the performance
downloaded from
http://compass.freescale.net/livelink/livelink?func=ll&objId=234609508&objAction=browse&viewType=1Before:
$ /opt/fsl-samples/g2d/g2d_test
Width 1920, Height 1088, Format RGBA, Bpp 32
---------------- g2d blit performance ----------------
g2d blit time 15566us, 64fps, 134Mpixel/s ........
g2d blending time 20672us, 48fps, 101Mpixel/s ........
g2d blend-dim time 13616us, 73fps, 153Mpixel/s ........
---------------- g2d clear performance ----------------
g2d clear time 8433us, 118fps, 247Mpixel/s ........
---------------- g2d rotation performance ----------------
90 rotation time 15366us, 65fps, 135Mpixel/s ........
180 rotation time 15374us, 65fps, 135Mpixel/s ........
270 rotation time 15373us, 65fps, 135Mpixel/s ........
g2d flip-h time 15373us, 65fps, 135Mpixel/s ........
g2d flip-v time 15372us, 65fps, 135Mpixel/s ...........
After:
$ /opt/fsl-samples/g2d/g2d_test
Width 1920, Height 1088, Format RGBA, Bpp 32
---------------- g2d blit performance ----------------
g2d blit time 2810us, 355fps, 743Mpixel/s ........
g2d blending time 4025us, 248fps, 518Mpixel/s ........
g2d blend-dim time 2740us, 364fps, 762Mpixel/s ........
---------------- g2d clear performance ----------------
g2d clear time 1846us, 541fps, 1131Mpixel/s ........
---------------- g2d rotation performance ----------------
90 rotation time 5234us, 191fps, 399Mpixel/s ........
180 rotation time 3176us, 314fps, 657Mpixel/s ........
270 rotation time 5248us, 190fps, 398Mpixel/s ........
g2d flip-h time 2765us, 361fps, 755Mpixel/s ........
g2d flip-v time 3179us, 314fps, 657Mpixel/s ...........
Signed-off-by: Robby Cai
16 Sep, 2015
1 commit
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The DDR initialization in plugin needs to update conformably with DCD.
Signed-off-by: Ye.Li
15 Sep, 2015
2 commits
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MMDC auto power saving timer can NOT be too small,
as enter/exit auto self-refresh mode too frequently
may introduce too many latency for MMDC access,
set it to 0x10, same as previous value on i.MX6.Signed-off-by: Anson Huang
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Add i.MX6QP SabreSD board support.
Signed-off-by: Anson Huang
04 Sep, 2015
1 commit
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The lpddr2 memsize of mx6ul_9x9_evk is 256MB, not 512M, so
the CS0_END should be 0x47, but not 0x4F.Signed-off-by: Peng Fan
02 Sep, 2015
1 commit
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Disable PFuze3000 low power mode during standby mode, otherwise,
if the power consumption exceed the threshold, PFuze will reboot.Signed-off-by: Anson Huang
01 Sep, 2015
2 commits
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Updated items:
memory set 0x307a0000 32 0x03040001 --> memory set 0x307a0000 32 0x01040001
This is just enable when LPDDR4 is enabled .memory set 0x307a0064 32 0x0040005e --> memory set 0x307a0064 32 0x00400046
T_RFC_MIN this should be: RU(260ns*528Mhz)/2=69 (0x45)memory set 0x307a00d0 32 0x00020001 --> memory set 0x307a00d0 32 0x00020083
PRE_CKE_X1024 be (500us*528Mhz/2)/1024 = 129, or 0x81memory set 0x307a00d4 32 0x00010000 --> memory set 0x307a00d4 32 0x00690000
DRAM_RSTN_X1024 (200us*528Mhz)/1024=104, or 0x68memory set 0x307a00e4 32 0x00090004 --> memory set 0x307a00e4 32 0x00100004
DEV_ZQINIT_X32 . Should be 16 clocksmemory set 0x307a0100 32 0x0908120a --> memory set 0x307a0100 32 0x09081109
T_FAW=(40ns*528Mhz)/2)=11memory set 0x307a0104 32 0x0002020e --> memory set 0x307a0104 32 0x0007020d
tXPDLL=24ns*528Mhz=13clocksFile:
MX7D_EVK_DDR3_1GB_32bit.dsTest result:
3 boards pass 2 days stress test.Signed-off-by: Ye.Li
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i.MX6UL-9x9-EVK board has PFUZE3000, so enable LDO
bypass support for this board.Signed-off-by: Anson Huang
20 Aug, 2015
1 commit
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This mx7d 19x19 lpddr2 arm2 board is based on 19x19 lpddr3 arm2 board
with DDR changed to 512M LPDDR2. We added DDR script for LPDDR2 and
a new u-boot build target: mx7d_19x19_lpddr2_arm2_configLPDDR2 script source: lpddr2_0_1.ds
Signed-off-by: Ye.Li
17 Aug, 2015
1 commit
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The i.mx6ul 9x9 EVK shares the same base board with 6ul 14x14 EVK
with two main changes on CPU board:
1. Change to use pfuze 3000.
2. Use 256MB LPDDR2 memory.This patch uses a macro CONFIG_6UL_9X9_LPDDR2 to distinguish the changes above,
basing on 14x14 EVK board level codes.The new build target for the 9x9 EVK: mx6ul_9x9_evk_config
Signed-off-by: Ye.Li
05 Aug, 2015
2 commits
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In LPSR mode, wdog will be reset when resume, need
to disable wdog powerdown timer to avoid system
reset after timeout setting of 16 seconds.Signed-off-by: Anson Huang
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For imx7d 12x12-lpddr3-arm2 board, when system enters LPSR
mode and waked up, ARM core will be reset and uboot needs to be
executed first, the LPSR register contains a resume entery,
if this entry is non-zero, then it means it is a resume from
LPSR mode, uboot plug in code needs to make DRAM exit from
retention mode then jump to the entry directly, otherwise,
it is a cold boot, normal boot process will be performed.Signed-off-by: Anson Huang
03 Aug, 2015
3 commits
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Since setup_waveform_file in different boards code have same implementation,
move setup_waveform_file to board common code. Also rename it to
board_setup_waveform_fileThis patch also fix a bug when using flush_cache. We should pass
'waveform_buf' to flush_cache, but not a string named 'addr'.Signed-off-by: Peng Fan
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Support draw image on E-ink screen.
1. The image format should be PGM-P5 raw data format.
2. The image should be named epdc_logo.pgm.
3. If no epdc_logo.pgm found in the first partition(FAT), will choose
to draw black border on the screen.
4. Default configuration is to draw image at pos (0,0). If 'splashpos'
env is set, will choose the pos from 'splashpos'.
5. The image size should not be bigger than screen total pixel size.
6. Implement board_setup_logo_file in board/freescale/common/epdc_setup.c
7. Introudce function prototype for board_setup_logo_file.Note: i.MX7D EPDC supports advanced mode and standard mode. Since current
PXP in uboot for i.MX7D not ready, only support standard mode now.
advanced and standard mode needs waveform firmware's support.Signed-off-by: Peng Fan
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Datasheet Rev-B defines standby voltage as 1V for i.MX7D, we add
25mV for board level IR drop.Signed-off-by: Anson Huang
31 Jul, 2015
1 commit
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As the HDMI splash screen feature is not well supported,
we should not set it to be the default display. In case,
users leave the 'panel' uboot environment variable empty
and connect the board with a HDMI monitor, the HDMI detect
funtion will work and enable the HDMI splash screen. So,
this patch disables HDMI detect function so that users
may only explicitly set the 'panel' variable to be 'HDMI'
to use HDMI splash screen.Signed-off-by: Peng Fan
Signed-off-by: Liu Ying
Signed-off-by: Ye.Li
22 Jul, 2015
2 commits
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This pin is missed to change in patch:
"MLK-11230 imx6: USB: Modify OTG ID pin pad setting to pull up"Should set it to pull down at default.
Signed-off-by: Ye.Li
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The SW1AB on PMIC is used for ARM_SOC_IN supply, set the standby voltage to
0.975V to save power when system is in DSM mode.Signed-off-by: Bai Ping