04 Feb, 2020
1 commit
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This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1021ASigned-off-by: Biwen Li
Signed-off-by: Priyanka Jain
18 Jan, 2020
2 commits
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These three clock functions don't use driver model and should be migrated.
In the meantime, create a new file to hold them.Signed-off-by: Simon Glass
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These functions relate to setting up the device tree for booting the OS.
The fdt_support.h header file supports similar functions, so move these
there.Signed-off-by: Simon Glass
03 Dec, 2019
1 commit
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A number of board function belong in init.h with the others. Move them.
Signed-off-by: Simon Glass
Reviewed-by: Tom Rini
27 Nov, 2019
1 commit
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The board_mmc_init() defined in board files is actually
doing same thing with the cpu_mmc_init() defined in
arch/arm/cpu/armv7/ls102xa/cpu.c. So drop it.Signed-off-by: Yangbo Lu
Reviewed-by: Priyanka Jain
29 Jul, 2019
1 commit
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Move dcu-related code to fsl_dcu_probe_common, keep in video_hw_init()
only legacy video stack (filling GraphicPanel struct etc.).Add wrappers for all init functions, that will let to provide
struct fb_info as an additional param (needed for further moving it from
the global scope to driver private data struct in DM converted driver).Signed-off-by: Igor Opaniuk
Reviewed-by: Oleksandr Suvorov
15 Mar, 2019
1 commit
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Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.Signed-off-by: Shengzhou Liu
Signed-off-by: Alison Wang
Reviewed-by: Prabhakar Kushwaha
07 Dec, 2018
1 commit
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I2C is used to access DDR SPD in the DDR initialization for SPL. In
i2c_write process, get_timer() will be called. In board_init_f for SPL,
timer_init() is not called before. The system counter is not enabled and
the counter frequency is not set to 12.5MHz in SPL. The parameters for
do_div() are zero too.It could not be found until CONFIG_USE_PRIVATE_LIBGCC is enabled in
default. When CONFIG_USE_PRIVATE_LIBGCC is enabled, U-Boot will use its
own set of libgcc functions. As the parameters for do_div() are zero,
__div0 will be called. Then the processor will stay in an endless loop
after calling hang().This patch will add timer_init() in board_init_f for SPL and fix a
series of issues it caused.Signed-off-by: Alison Wang
Reviewed-by: York Sun
27 Sep, 2018
1 commit
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Remove the old implementation in order to enable DM for sata
Signed-off-by: Peng Ma
Reviewed-by: York Sun
07 May, 2018
1 commit
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.Signed-off-by: Tom Rini
02 May, 2018
1 commit
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freescale.com domain is no longer reachable, so switch the
maintainers' emails to nxp.com domain instead.Signed-off-by: Fabio Estevam
28 Apr, 2018
1 commit
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We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.Signed-off-by: Tom Rini
11 Sep, 2017
1 commit
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CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.Signed-off-by: Ashish Kumar
Signed-off-by: Prabhakar Kushwaha
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: York Sun
06 Jun, 2017
1 commit
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The declarations should not be in common.h. Move them to the arch-specific
headers.Signed-off-by: Simon Glass
[trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)]
Signed-off-by: Tom Rini
15 Apr, 2017
1 commit
14 Apr, 2017
1 commit
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Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB
and convert it to Kconfig.Signed-off-by: Sanchayan Maity
Reviewed-by: Stefan Agner
Reviewed-by: Alison Wang
13 Apr, 2017
1 commit
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This function name shadows a global name but is in fact different. This
is very confusing. Rename it to help with the following refactoring.Signed-off-by: Simon Glass
06 Apr, 2017
3 commits
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By making dram_init_banksize() return an error code we can drop the
wrapper. Adjust this and clean up all implementations.Signed-off-by: Simon Glass
Reviewed-by: Stefan Roese -
At present we cannot use this function as an init sequence call without a
wrapper, since it returns the RAM size. Adjust it to set the RAM size in
global_data instead, and return 0 on success.Signed-off-by: Simon Glass
Reviewed-by: Stefan Roese -
It looks like only cm5200 and tqm8xx use this feature, so we don't really
need it in generic code. Drop it and have the users access gd->board_type
directly.Signed-off-by: Simon Glass
Reviewed-by: Stefan Roese
01 Feb, 2017
1 commit
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Set cpo_sample as suggested by the driver
"WARN: pls set popts->cpo_sample = 0x58 in /ddr.c to optimize
cpo".Signed-off-by: York Sun
CC: Shengzhou Liu
24 Jan, 2017
1 commit
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Introduce board/freescale/common/Kconfig so that we have a single place
for CONFIG options that are shared between ARM and PowerPC NXP platforms.Cc: York Sun
Signed-off-by: Tom Rini
Reviewed-by: York Sun
06 Dec, 2016
1 commit
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- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.Signed-off-by: Shengzhou Liu
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun
22 Nov, 2016
1 commit
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Change core clock to 1.2GHz in the configurations for SD and NAND boot.
Signed-off-by: Yuan Yao
Reviewed-by: York Sun
07 Oct, 2016
1 commit
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Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and
ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First
stage of u-boot can run faster after that. There is a description
about skip lowlevel init in board/freescale/ls1021atwr/README.Signed-off-by: Xiaoliang Yang
Reviewed-by: York Sun
15 Sep, 2016
2 commits
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As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
Move forward the basic non-secure access enable operation, so the
subsequent individual device access permission can override it.
And collect the dispersed callers in board level, and then move
them to SoC level.Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun
27 Jul, 2016
1 commit
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This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.Tested on LS1021aQDS, LS1021aTWR.
Signed-off-by: Wang Dongsheng
Signed-off-by: Hongbo Zhang
Reviewed-by: York Sun
04 Jun, 2016
1 commit
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This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun
25 Feb, 2016
3 commits
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The initialization for smmu and stream id is moved into the common soc
code.Signed-off-by: Alison Wang
Reviewed-by: York Sun -
As the QE firmware struct is shared with Fman, move the header file
out of drivers/qe/.Signed-off-by: Gong Qianyu
Reviewed-by: York Sun -
As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported
in SD boot now. For the customer's demand, QSPI needs to be supported
in SD boot too.This patch adds QSPI or IFC support in SD boot according to the
corresponding defconfig. For detail, ls1021aqds_sdcard_ifc_defconfig
is used to support IFC in SD boot and ls1021aqds_sdcard_qspi_defconfig
is used to support QSPI in SD boot.Signed-off-by: Alison Wang
Reviewed-by: York Sun
28 Jan, 2016
1 commit
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Chain of Trust is enabled for ARM platforms (LS1021 and LS1043).
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)Signed-off-by: Aneesh Bansal
Acked-by: Ruchika Gupta
Reviewed-by: York Sun
15 Jan, 2016
1 commit
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With format-security errors turned on, GCC picks up the use of sprintf with
a format parameter not being a string literal.Simple uses of sprintf are also converted to use strcpy.
Signed-off-by: Ben Whitten
Acked-by: Wolfgang Denk
Reviewed-by: Tom Rini
14 Dec, 2015
1 commit
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Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao
Reviewed-by: York Sun
30 Oct, 2015
2 commits
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Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun -
Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.Signed-off-by: Mingkai Hu
Signed-off-by: Hou Zhiqiang
Signed-off-by: Gong Qianyu
Reviewed-by: York Sun
02 Sep, 2015
2 commits
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DEVDISRn registers provides a mechanism for gating clocks of IP blocks
that are not used. Here we implement hwconfig option to allow users
to disable unused peripherals on the board.For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts,
User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma"
in hwconfig, thus ESDHC controller & eDMA/qDMA will be clock gated to
save more power.Signed-off-by: Zhuoyu Zhang
Reviewed-by: York Sun -
Replace the DMACTRL[LE] hack with recommended settings
for ETSECDMAMCR to get the same end effect - obtaining
big-endian buffer descriptors and frame data for eTSEC.
The reset / default value for ETSECDMAMCR is preserved,
excepting the BD and FR bits which are cleared to enable
the BE mode in accordance with the H/W specifications.Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA"
Signed-off-by: Claudiu Manoil
Acked-by: Alison Wang
Tested-by: Alison Wang
Reviewed-by: York Sun
04 Aug, 2015
1 commit
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On LS1021A Rev2.0, OCRAM's security level needs to be changed to
non-secure access for SD boot. This patch will allow OCRAM
access permission as R/W in SPL.Signed-off-by: Alison Wang
Reviewed-by: York Sun