10 Apr, 2015
9 commits
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This function should not return a value.
Signed-off-by: Simon Glass
Acked-by: Thomas Chou -
Work_92105 from Work Microwave is an LPC3250-
based board with the following features:
- 64MB or 128MB SDR DRAM
- 1 GB SLC NAND, managed through MLC controller.
- Ethernet
- Ethernet + PHY SMSC8710
- I2C:
- EEPROM (24M01-compatible)
- RTC (DS1374-compatible)
- Temperature sensor (DS620)
- DACs (2 x MAX518)
- SPI (through SSP interface)
- Port expander MAX6957
- LCD display (HD44780-compatible), controlled
through the port expander and DACsThis board has SPL support, and uses the LPC32XX boot
image format.Signed-off-by: Albert ARIBAUD (3ADEV)
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Reviewed-by: Jagannadha Sutradharudu Teki
Signed-off-by: Albert ARIBAUD (3ADEV) -
This driver only supports Driver Model, not legacy model.
Signed-off-by: Albert ARIBAUD (3ADEV)
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Signed-off-by: Albert ARIBAUD (3ADEV)
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The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.The SPL framework is supported.
Signed-off-by: Albert ARIBAUD (3ADEV)
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Signed-off-by: Albert ARIBAUD (3ADEV)
07 Apr, 2015
1 commit
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Back in fc46bae a "clean up" was introduced that intended to reconcile
some of the AM335x codepaths based on how AM43xx operates.
Unfortunately this introduced a regression on the DDR2 platforms. This
was un-noticed on DDR3 (everything except for Beaglebone White) as we
had already populated sdram_config correctly in sequence. This change
brings us back to the older behavior and is fine on all platforms.Tested on Beaglebone White, Beaglebone Black and AM335x GP EVM
Reported-by: Matt Ranostay
Signed-off-by: Tom Rini
06 Apr, 2015
6 commits
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Add backlight enable GPIO, and delay needed for panel powerup
via FIMD DT node.Signed-off-by: Ajay Kumar
Reviewed-by: Simon Glass
Tested-by: Simon Glass
Signed-off-by: Minkyu Kang -
Now that parade driver supports reading SLP and RST GPIO
from DT, specify the same in parade DT node.Signed-off-by: Ajay Kumar
Reviewed-by: Simon Glass
Tested-by: Simon Glass
Signed-off-by: Minkyu Kang -
Now that the exynos_fb driver supports handling backlight GPIO
via DT, specify pwm output property via FIMD DT node.Signed-off-by: Ajay Kumar
Reviewed-by: Simon Glass
Tested-by: Simon Glass
Signed-off-by: Minkyu Kang -
The existing setting for rpll_sdiv generates 70.5Mhz RPLL
video clock to drive 1366x768 panel on peach_pit.This clock rate is not sufficient to drive 1920x1080 panel on peach-pi.
So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock
which can drive peach-pi LCD.This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD
divider at IP level will get set to 1(the required divider setting
will be calculated and set by exynos_fimd_set_clock()) and hence
peach-pit LCD still works fine.Signed-off-by: Ajay Kumar
Reviewed-by: Simon Glass
Tested-by: Simon Glass
Signed-off-by: Minkyu Kang -
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by
exynos video driver.Signed-off-by: Ajay Kumar
Reviewed-by: Simon Glass
Tested-by: Simon Glass
Signed-off-by: Minkyu Kang -
Commit 2e82e9252695a612ab0cbf40fa0c7368515f6506 'Exynos: Clock: Cleanup
soc_get_periph_rate' introduced a bug in I2C config. This patch makes cros_ec
keyboard working again on Samsung Chromebook (snow).Changes in V2: reorder lines as requested by Joonyoung Shim.
Signed-off-by: Guillaume GARDET
Cc: Akshay Saraswat
Cc: Minkyu Kang
Cc: Joonyoung Shim
Reviewed-by: Simon Glass
Tested-by: Simon Glass
Signed-off-by: Minkyu Kang
03 Apr, 2015
11 commits
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Conflicts:
board/armltd/vexpress64/vexpress64.cSigned-off-by: Tom Rini
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ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache).
This change adds functions required for controlling SLC:
* slc_enable/disable
* slc_flush/invalidateFor now we just disable SLC to escape DMA coherency issues until either:
* SLC flush/invalidate is supported in DMA APIin U-Boot
* hardware DMA coherency is implemented (that might be board specific
so probably we'll need to have a separate Kconfig option for
controlling SLC explicitly)Signed-off-by: Alexey Brodkin
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Signed-off-by: Alexey Brodkin
Cc: Masahiro Yamada
Cc: Simon Glass -
Now when all infrastructure in ARC is ready for it let's switch ARC UART
to driver model.Signed-off-by: Alexey Brodkin
Cc: Masahiro Yamada
Cc: Simon Glass -
[1] Fix misspeling in ARC_CACHE_LINE_SHIFT dependency, now cache-line
lenth selection is correctly enabled if either I$ or D$ are enabled.[2] Add dummy entry to target list to make sure target type is always
mentioned in defconfig. Otherwise defconfig for the first target in the
list will not have target name and later on with addition of the new
target on top of the list in Kconfig will lead to corrupted
configuration expanded from defconfig.Signed-off-by: Alexey Brodkin
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As discussed on mailing list we're drifting away from
CONFIG_SYS_GENERIC_GLOBAL_DATA in favour to use of board_init_f_mem()
for global data.So do this for ARC architecture.
Signed-off-by: Alexey Brodkin
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Intention behind this work was elimination of as much assembly-written
code as it is possible.In case of ARC we already have relocation fix-up implemented in C so why
don't we use C for U-Boot copying, .bss zeroing etc.It turned out x86 uses pretty similar approach so we re-used parts of
code in "board_f.c" initially implemented for x86.Now assembly usage during init is limited to stack- and frame-pointer
setup before and after relocation.Signed-off-by: Alexey Brodkin
Cc: Simon Glass -
This separation makes maintenance of code easier because those low-level
interrupt- or exception handling routines are pretty static and usually
require not much care while start-up code is a subject of modifications
and enhancements.Signed-off-by: Alexey Brodkin
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Even though ARCompact and ARCv2 are not binary compatible most of
assembly instructions are used in both. With this change we'll get rid
of duplicate code.Still IVTs are implemented differently so we're keeping them in separate
files.Signed-off-by: Alexey Brodkin
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always
Make both invalidate_icache_all() and invalidate_dcache_all() available
even if U-Boot is configured with CONFIG_SYS_DCACHE_OFF and/or
CONFIG_SYS_ICACHE_OFF.This is useful because configuration of U-Boot may not match actual
hardware features. Real board may have cache(s) but for some reason we
may want to run U-Boot with cache(s) disabled (for example if some
peripherals work improperly with existing drivers if data cache is
enabled). So board may start with cache(s) enabled (that's the case for
ARC cores with built-in caches) but early in U-Boot we disable cache(s)
and make sure all contents of data cache gets flushed in RAM.Signed-off-by: Alexey Brodkin
01 Apr, 2015
8 commits
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Enable SPL support for at91sam9n12ek boards, now it supports
boot up from NAND flash, serial flash.Signed-off-by: Bo Shen
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Enable SPL support for at91sam9x5ek board. Now, it supports
boot up from NAND flash and SPI flash.Signed-off-by: Bo Shen
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Supports boot up from NAND flash with software ECC eanbled.
And supports boot up from SD/MMC card with FAT file system.As the boot from SD/MMC card with FAT file system, the BSS
segment is too big to fit into SRAM, so, use the lds to put
it into SDRAM.Signed-off-by: Bo Shen
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Config MCKR according to the datasheet sequence, or else it
will cause the MCKR configuration failed.Remove timeout checking for clock configuration, if configure
the clock failed, let the system hang while not run in wrong
clock configuration.Signed-off-by: Bo Shen
Tested-by: Heiko Schocher -
To facilitate changing lowlevel_init to become s_init, move the current
contents of s_init into board_init_f and add the rest of what
board_init_f does here.
In order to compile clean without CONFIG_SKIP_LOWLEVEL_INIT set, leave an
empty stub of s_init(). It can be removed when lowlevel_init becomes s_init.Cc: Bo Shen
Cc: Andreas Bießmann
Tested-by: Matt Porter on sama5d3_xplained
Signed-off-by: Tom Rini
[rebased on current master, leave s_init() as empty stub]
Signed-off-by: Andreas Bießmann -
The commit 8dfafdd (Introduce common timer functions), add common
timer functions, we can use them directly.Signed-off-by: Bo Shen
[rebase on current master]
Sigend-off-by: Andreas Bießmann -
Signed-off-by: Bo Shen
[rebase on current master]
Signed-off-by: Andreas Bießmann
31 Mar, 2015
5 commits
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Even the 8-bit case needs KBCB configured, as pin D7 is located in this
pingroup.Please note that pingroup ATC seems to come out of reset with its
config set to NAND so one needs to explicitly configure some other
function to this group in order to avoid clashing settings which is
outside the scope of this patch.Signed-off-by: Lucas Stach
Signed-off-by: Marcel Ziswiler
Tested-by: Marcel Ziswiler
Signed-off-by: Tom Warren -
A while ago I got Russell to change the machine type of our Colibri T20
from COLIBRI_TEGRA2 to COLIBRI_T20 which at least in parts is also
reflected in his machine registry:http://www.arm.linux.org.uk/developer/machines/list.php?id=3323
For us it is really very beneficial to actually still be able to boot
downstream L4T kernel with its working hardware accelerated
graphics/multimedia stack albeit it being proprietary/closed-source.Signed-off-by: Marcel Ziswiler
Acked-by: Stephen Warren
Signed-off-by: Tom Warren -
In accordance with our other modules supported by U-Boot and as agreed
upon for Apalis/Colibri T30 get rid of the carrier board in the board/
configuration/device-tree naming.While at it also bring the prompt more in line with our other products.
Signed-off-by: Marcel Ziswiler
Signed-off-by: Tom Warren -
This allows selection between CSI and DSI_B on the MIPI pads.
Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren
