06 May, 2014
1 commit
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- expand the condition with CONFIG_OF_CONTROL
Signed-off-by: Stephan Linz
Acked-by: Simon Glass
Signed-off-by: Michal Simek
02 May, 2014
1 commit
30 Apr, 2014
1 commit
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Signed-off-by: Masahiro Yamada
Cc: Nobuhiro Iwamatsu
Acked-by: Nobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu
29 Apr, 2014
2 commits
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Most of the I2C slaves support accesses in the typical style
that is : read/write series of bytes at particular address offset.
These transactions look like:"
(1) START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP"However there are certain devices which support accesses in
terms of the transactions as follows:
(2) "START:Address:Tx:Txdata[0..n1]:Clock_stretching:
RESTART:Address:Rx:data[0..n2]"
Here Txdata is typically a command and some associated data,
similarly Rxdata could be command status plus some data received
as a response to the command sent.Type (1) transactions are currently supportd in the
i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs,
RTC, etc fall in this category.To handle type (2) along with type (1) transactions,
i2c_read() function has been modified.Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal -
This driver needs a data structure in SRAM before SDRAM is available.
This is not alway the case using .data section. Moving this data
structure to global_data guarantees it is writable.Signed-off-by: York Sun
CC: Troy Kisky
26 Apr, 2014
4 commits
25 Apr, 2014
2 commits
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Signed-off-by: Alexey Brodkin
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With 32 milliseconds delay on some boards EEMPROM got written inconsistently.
With 64 msec all of our existig boards show properly written EEPROM.Cc: Tom Rini
Signed-off-by: Alexey Brodkin
24 Apr, 2014
4 commits
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This patch adds support for the new PMC440 hardware revision 1.4.
The board now uses Micrel KSZ9031 phys.Add missing i2c initialization before reading bootstrap eeprom.
Fix a couple of coding style issues.
Make local functions static.
Signed-off-by: Matthias Fuchs
Signed-off-by: Stefan Roese -
add support for the ids8313 board.
CPU: e300c3, MPC8313, Rev: 2.1 at 396 MHz, CSB: 132 MHz
I2C: ready
SPI: ready
DRAM: 128 MiB (DDR2, 32-bit, ECC off, 264 MHz)
Flash: 8 MiB
NAND: 128 MiB
Net: TSEC0, TSEC1 [PRIME]public key on NOR flash start
Signed-off-by: Heiko Schocher
Signed-off-by: Kim Phillips -
mpc831x has no muram, so muram cannot be used for bootcounter
function.Signed-off-by: Heiko Schocher
Signed-off-by: Kim Phillips -
create vendor board directory ids and move ids8247 board to it.
Signed-off-by: Heiko Schocher
Cc: Wolfgang Denk
Signed-off-by: Kim Phillips
23 Apr, 2014
25 commits
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This reverts commit a8b993eb81c142a439c24b871a2317f765fe5397.
Commit a8b993eb claims it fixes u-boot.lds rule by replacing
$(call if_changed) with $(call filechk).But the problem had already been fixed by commit 395e60cd
a few days before commit a8b993eb was posted.There is no reason to apply commit a8b993eb. What is worse is
$(call filechk) is too strong to fix the problem and looks weird.Date of the two patches:
[1] commit 395e60cdc292dc0183c6867d34b43f14a373df55
Author: Masahiro Yamada
AuthorDate: Wed Apr 9 20:10:43 2014 +0900
Commit: Tom Rini
CommitDate: Fri Apr 11 10:08:42 2014 -0400
replaces $(call if_changed) -> $(call if_changed_dep)[2] commit a8b993eb81c142a439c24b871a2317f765fe5397
Author: Jon Loeliger
AuthorDate: Tue Apr 15 16:09:37 2014 -0500
Commit: Tom Rini
CommitDate: Fri Apr 18 16:14:16 2014 -0400
replaces $(call if_changed) -> $(call filechk)A conflict must have happened when applying [2], but somehow it was
applied, sadly.Signed-off-by: Masahiro Yamada
Cc: Jon Loeliger
Cc: Andreas Bießmann
Cc: Tom Rini -
ar8031 has the same config steps with ar8021, so change its
config func to ar8021_config instead of genphy_config.Signed-off-by: Zhao Qiang
Reviewed-by: York Sun -
Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND boot, fix it.Signed-off-by: Shaohui Xie
Reviewed-by: York Sun -
Updated the RCW for rev2.0 which uses new frequency settings as below:
Clock Configuration:
CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz,
CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz,
CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667MHz,
CCB:733.333 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz
FMAN1: 733.333 MHz
FMAN2: 733.333 MHz
QMAN: 366.667 MHz
PME: 533.333 MHzRemove workaround of IFC bus speed and SERDES A-006031 of rev1.0.
Signed-off-by: Shaohui Xie
Reviewed-by: York Sun -
B4420 is a personality of B4860.
It should have same FM1_CLK_SEK and FM1_CLK_SHIFT as B4860Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
- update readme.
- add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315
ucode from NOR/NAND/SPI/SD/REMOTE.
- update cpld vbank with SW3[5:7]=000 as default vbank0 instead of
previous SW3[5:7]=111 as default vbank.
- fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control
to u-boot.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers
control to u-boot.Signed-off-by: Shengzhou Liu
[York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH]
Reviewed-by: York Sun -
Adds support for clock sourcing from sysclk(100MHz) for usb
on T104xRDB and T1040QDS. This requires changing reference divisor
and multiplication factor to derive usb clock from sysclk.Signed-off-by: Nikhil Badola
Reviewed-by: York Sun -
T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode.
In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock
(100MHz) to the following PLLs:
• Platform PLL
• Core PLLs
• USB PLL
• DDR PLL, etcThe cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or
DIFF_SYSCLK (differential) is selected as the clock input to the chip.get_sys_info has been enhanced to add the diff_sysclk so that the
various drivers can be made aware of ths diff sysclk configuration and
act accordingly.Other changes:
-single_src to ddr_refclk_sel, as it is use for checking ddr reference clock
-Removed the print of single_src from get_sys_info as this will be
-printed whenever somebody calls get_sys_info which is not appropriate.
-Add print of single_src in checkcpu as it is called only once during initializationSigned-off-by: Poonam Aggrwal
Signed-off-by: Priyanka Jain
Signed-off-by: Vijay Rai
Reviewed-by: York Sun -
There should be a break for case PHY_INTERFACE_MODE_SGMII, otherwise it
will fall into case PHY_INTERFACE_MODE_RGMII.Signed-off-by: Shaohui Xie
Reviewed-by: York Sun -
u-boot binary size for Freescale mpc8536DS platforms is 512KB.
This has been reached to upper limit of the platforms and causig
linker error. So increase the u-boot binary size to 768KB.Signed-off-by: Haijun Zhang
Reviewed-by: York Sun -
U-boot binary size has been increased from 512KB to 768KB.
So update CONFIG_SYS_MONITOR_LEN to reflect the same.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
It is not necessary for bootpg to be present at text + 512KB.
With increase of u-boot size (768KB), bootpg section's address
cannot be fixed.Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordinglySigned-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Add support of 2 stage NAND boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordinglySigned-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Objective of this target to have concatenate binary having
- SPL binary in PBL command format
- U-boot binarySigned-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Add support of loading image, binary for MMC and SPI during SPL boot.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
SPI driver perform its operation(read/write) on 64KB buffer chunk for data
greater than 64KB. This buffer chunk is allocated from system heap.During SPL boot, 768KB of data is read from SPI flash.
Here, heap size may not be sufficient enough to full-fill 64KB buffer
requirement of SPI driver. So break down u-boot read operation at 8KB of chunk.Also, fix a warning i.e. "unused variable buf" during CONFIG_FSL_CORENET
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
nand_spl_load_image() can also be used for non TPL framework.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Before parsing LAW table i.e. init_law, boot loader should disable all
previous LAWs except DDR LAWs which has been created by previous
pre boot loader during DDR initialization.Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Current SPL code base has BSS section placed after reset_vector. This means
they have to relocate to use the global variables. This put an implicit
requirement of having SPL size = Memory/2.To avoid relocation:
- Move bss_section within SPL range
- Modify relocate_code()Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
SPL linker has fix location of bootpg and reset vector with respect to text base.
It is not necessary to have fixed locations.Avoid such hardcoding.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to
CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence
both are same. This cause compilation error.So LAW_EN define outside of configs
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun
