07 Jun, 2014

6 commits


02 Jun, 2014

1 commit


28 May, 2014

3 commits


27 May, 2014

2 commits


25 May, 2014

5 commits

  • On Mon, 2014-05-05 at 14:18 +0200, Stefan Roese wrote:
    > > + case 1:
    > > +#if CONFIG_MMC1_PG

    > Are you sure that this is correct and shouldn't be:
    >
    > +#ifdef CONFIG_MMC1_PG
    >
    > ?

    It's "correct" in so far as it works (the boards.cfg config stuff
    #defines things to 1), but I think you are right that it isn't the
    preferred style. But...

    > A quick scan through this patch series shows that this define
    > is not set at all. Perhaps its outdated? Or is it used to support
    > some other sunxi SoC? Not sure, perhaps it should be removed for
    > now.

    ...I had thought that it was to support some other board which wasn't
    being upstreamed right now, so eventually useful and harmless for now,
    but I've just checked and it isn't actually used by any of the boards in
    u-boot-sunxi.git. So rather than fix it to use #ifdef lets drop it.
    Rather than resend the entire series, here is v5.1 of this patch.

    > Other than this please add my:
    >
    > Reviewed-by: Stefan Roese

    Thanks!

    8From 20704e35a41664de5f516ed0e02981ac06085102 Mon Sep 17 00:00:00 2001
    From: Ian Campbell
    Date: Fri, 7 Mar 2014 04:29:39 +0000
    Subject: [PATCH v5.1 7/8] sunxi: mmc support

    This adds support for the MMC controller on the Allwinner A20 (sun7i)
    processor.

    Signed-off-by: Henrik Nordstrom
    Signed-off-by: Luke Leighton
    Signed-off-by: Oliver Schinagl
    Signed-off-by: Wills Wang
    Signed-off-by: Ian Campbell
    Reviewed-by: Marek Vasut
    Reviewed-by: Stefan Roese
    Cc: Tom Cubie
    Cc: Aaron Maoye
    Cc: Pantelis Antoniou
    Reviewed-by: Tom Rini

    Ian Campbell
     
  • Add support for the GMAC Ethernet controller on Allwinner A20 (sun7i)
    processors. Enable for the Cubietruck.

    Signed-off-by: Chen-Yu Tsai
    Signed-off-by: Jens Kuske
    Signed-off-by: Ian Campbell
    Reviewed-by: Marek Vasut
    Reviewed-by: Tom Rini

    Ian Campbell
     
  • Signed-off-by: Oliver Schinagl
    Signed-off-by: Jens Kuske
    Signed-off-by: Ian Campbell
    Reviewed-by: Tom Rini
    Reviewed-by: Marek Vasut

    Ian Campbell
     
  • This patch adds generic board, start of day and basic build system support for
    the Allwinner A20 (sun7i) processor. This code will not been compiled until the
    build is hooked up in a later patch. It has been split out to keep the patches
    manageable.

    Signed-off-by: Adam Sampson
    Signed-off-by: Aleksei Mamlin
    Signed-off-by: Alexandru Gagniuc
    Signed-off-by: Chen-Yu Tsai
    Signed-off-by: Emilio López
    Signed-off-by: Hans de Goede
    Signed-off-by: Henrik Nordstrom
    Signed-off-by: Jens Kuske
    Signed-off-by: Luc Verhaegen
    Signed-off-by: Luke Leighton
    Signed-off-by: Oliver Schinagl
    Signed-off-by: Patrick Wood
    Signed-off-by: Stefan Roese
    Signed-off-by: Wills Wang
    Signed-off-by: Ian Campbell
    Reviewed-by: Marek Vasut
    Cc: Tom Cubie
    Reviewed-by: Tom Rini

    Ian Campbell
     
  • Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM
    issues with newer silicon (1.1). This register was added in revision
    4 of the Vybrid Reference Manual.

    Signed-off-by: Stefan Agner

    Stefan Agner
     

24 May, 2014

11 commits


23 May, 2014

5 commits


21 May, 2014

1 commit


20 May, 2014

2 commits


17 May, 2014

4 commits

  • Tom Rini
     
  • In the earlier patches, the SPL/TPL fraamework was introduced.
    For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
    SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
    the DDR according to the SPD and loads the final uboot image into DDR, then
    jump to the DDR to begin execution.

    For NAND booting way, the nand SPL has size limitation on some board(e.g.
    P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the
    dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
    loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
    and loads the final uboot image into DDR,then jump to the DDR to begin execution.

    This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI
    flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
    Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
    execute, so the section .resetvec is no longer needed.

    Signed-off-by: Prabhakar Kushwaha
    Reviewed-by: York Sun

    Prabhakar Kushwaha
     
  • T104xrdb has several sleep management signals that are used for deep
    sleep. They are enabled by OS to enter deep sleep and should be
    disabled by u-boot when cores wake up.

    Signed-off-by: Tang Yuantian
    Reviewed-by: York Sun

    Tang Yuantian
     
  • According to AN3638, CRC of NXID v1 is at the end of the
    256-byte I2C memory. The wrong CRC32 offset prevents Uboot
    from reading system information from EEPROM. No NXID v0 is
    being used on Freescale boards.

    Signed-off-by: Ebony Zhu
    Reviewed-by: York Sun

    Ebony Zhu