10 Oct, 2014
9 commits
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The lines COL (collision detect) and CRS (carrier sense) needs to be connected
and muxed to the CPSW MAC for a proper function in half-duplex Mode of the
interface.Signed-off-by: Hannes Petermaier
Cc: Tom Rini -
fix broken SPI access by adding/activating BOARD_EARLY_INIT_F
functionality and calling spi_init_f() from there.Signed-off-by: David Müller
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Fix typo of commit d4e53f063dd25e071444b87303573e7440deeb89.
i2c2 pullup resisters are controlled by bit 0 of CONTROL_PROG_IO1.
It's value after reset is 0x00100001.In order to clear bit 0, original code write 0xfffffffe to
CONTROL_PROG_IO1 and toggle almost all default values.Original code affect following:
* disable i2c1 pullup resisters
* increase far end load setting for many modules
* setup invalid SC/LB combinationSigned-off-by: Alexander Kochetkov
CC: Tom Rini
CC: Steve Kipisz -
These boards have been orphaned for more than 6 months.
Signed-off-by: Masahiro Yamada
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These boards have been orphaned for more than 6 months.
Signed-off-by: Masahiro Yamada
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This board has been orphaned for more than 6 months.
It is the last board defining CONFIG_APM821XX.
The code inside #ifdef CONFIG_APM821XX should be removed too.Signed-off-by: Masahiro Yamada
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This board has been orphaned for more than 6 months.
Signed-off-by: Masahiro Yamada
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These boards have been orphaned for more than 6 months.
Signed-off-by: Masahiro Yamada
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On OMAP platforms, SATA controller provides the SCSI subsystem
so implement scsi_init().Get rid of the unnecessary sata_init() call from dra7xx-evm
and omap5-uevm board files.Signed-off-by: Roger Quadros
08 Oct, 2014
1 commit
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In order for the gmac nic to work reliable on the Bananapi, we need to set
bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" of the GMAC clk register
(0x01c20164) to 3.Without this about 9 out of 10 ethernet packets get lost, with this setting
there is no packet loss.So far setting these bits is only necessary on the Bananapi, so this commit
solves this with a bit of #ifdef CONFIG_BANANAPI code. If in the future we
need to do something similar for other boards, we can create a specific
CONFIG_FOO option for this then.Reported-by: Karsten Merker
Signed-off-by: Hans de Goede
Tested-by: Karsten Merker
Tested-by: Zoltan HERPAI
Tested-by: Tony Zhang
Acked-by: Ian Campbell
07 Oct, 2014
2 commits
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Removed settings in unsupported register fields. They didn’t
do anything, and in most cases, were not documented in the
reference manual.Changed register settings to comply with JEDEC required values.
Changed timing parameters because they included full clock
periods that were doing nothing.Signed-off-by: Anthony Felice
[rebased on v2014.10-rc2]
Signed-off-by: Stefan Agner
06 Oct, 2014
5 commits
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Move icache_enable() and dcache_enable() function calls from
board code into the CPU code and into the enable_caches()
function. This is how the cache enabling code was designed
to work.Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc: Marek Vasut
Cc: Tom Rini
Cc: Albert Aribaud
Cc: Wolfgang Denk
Acked-by: Pavel Machek -
The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Cosmetic change to the checkboard() function output. Align the
output with the rest of initial output produced by U-Boot.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
The bi_boot_params must point to offset 0x100 in DRAM. Make it so.
Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek -
Add some stub defines, which are used by the clock code, but are
missing from the auto-generated header file for the SoCFPGA family.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Dinh Nguyen
Acked-by: Pavel Machek
26 Sep, 2014
3 commits
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LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.Signed-off-by: York Sun
CC: Alison Wang
25 Sep, 2014
11 commits
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Spin table is at the very beginning of boot code. Each core has an individual
release address within the spin table, the ft_cpu_setup fn updates the
"cpu-release-addr" property of each cpu node with the corresponding release
address.Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.
Signed-off-by: York Sun
Signed-off-by: Arnab Basu -
DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).Signed-off-by: York Sun
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The macro MIN, MAX is defined as the aliase of min, max,
respectively.Signed-off-by: Masahiro Yamada
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Since commit ddaf5c8f3030050fcd356a1e49e3ee8f8f52c6d4
(patman: RunPipe() should not pipe stdout/stderr unless asked),
Patman spits lots of "Invalid MAINTAINERS address: '-'"
error messages for patches with global changes.
It takes too long for Patman to process them.Anyway, "M: -" does not carry any important information.
Rather, it is just like a place holder in case of assigning
a new board maintainer. Let's comment out.This commit can be reproduced by the following command:
find . -name MAINTAINERS | xargs sed -i -e '/^M:[[:blank:]]*-$/s/^/#/'
Signed-off-by: Masahiro Yamada
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The "S: Orphan" in MAINTAINERS means that the maintainer in the
"M:" field is unreachable (i.e. the email address is not working).
(Refer to the definition of "Orphan" adopted in U-Boot
in the log of commit 31f1b654b2f395b69faa5d0d3c1eb0803923bd3b,
"boards.cfg: move boards with invalid emails to Orphan")For patch files adding global changes, scripts/get_maintainer.pl
adds bunch of such invalid email addresses, which results in
tons of annoying bounce emails.This commit can be reproduced by the following command:
find . -name MAINTAINERS | xargs sed -i -e '
/^M:[[:blank:]]/ {
N
/S:[[:blank:]]Orphan/s/^/#/
}
'Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass -
Each CPU of PowerPC has its default linker script under the CPU
directory, except mpc8xx.Every mpc8xx board has its own linker script under the board
directory, resulting in lots of duplication of linker scripts.I notice eight mpc8xx boards have the same linker script.
We can decrease the number of linker scripts by putting a single
default linker script, arch/powerpc/cpu/mpc8xx/u-boot.lds.Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denk
Acked-by: Stefan Roese -
T1042QDS (T1042 is T1040 Personality without L2 switch) supports following
sgmii interfaces with serdes protocol 0xA7
-SGMII-MAC3 on Lane B - slot 7
-SGMII-MAC5 on Lane H - slot 7
-SGMII2.5G-MAC1 on Lane C - slot 6
-SGMII2.5G-MAC2 on Lane D - slot 5Add support of above sgmii interfaces
Signed-off-by: Priyanka Jain
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DDR-ODT require cfg_dram_type switch set properly as per DDR type.
T1040RDB, T1042RDB boards have DDR3L type DDR, so cfg_dram_type
should be set to OFF for DDR3L
Update t104xrdb/README for switch settingSigned-off-by: Priyanka Jain
Reviewed-by: York Sun -
T1042RDB is a Freescale reference board that hosts the T1042 SoC
(and variants). The board is similar to T1040RDB, T1042 is a reduced
personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).T1042RDB is configured with serdes protocol 0x86 which can support
following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
DTSEC1, DTSEC2 are not connected on board.This Patch
- add T1042RDB support
- updates README file for T1042RDB details and update commands for switching
to alternate banks from vBank0 to vBank4 and vice versaThis patch also does minor clean ups for fdt defines for T1042RDB and
T1042RDB_PI boardSigned-off-by: Vijay Rai
Signed-off-by: Priyanka Jain
Reviewed-by: York Sun -
This patch adds support of rcw for T1042RDB, it makes following changes :
- Adds t1042_rcw.cfg file for serdes protocol 0x86 for T1042RDB
- Renames t1042_pi_rcw.cfg file from t1042_rcw.cfg and also updates
comments for valid serdes protocol which is 0x06
- Also updates CONFIG_SYS_FSL_PBL_RCW for T1042RDBSigned-off-by: Vijay Rai
Signed-off-by: Priyanka Jain
Reviewed-by: York Sun -
LS2085a has 2 regions in system memory map. Region1 is default map from
where system boots. Once u-boot is moved to DDR, IFC is re-mapped to
Region2.So, update gd->env_addr to reflect correct address.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun
24 Sep, 2014
1 commit
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MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
across multiple transactions. This is set up by embedding the GPIO information
in the CS value:cs = (cs | gpio << 8)
This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is required, invoking "sf probe " will not work, because
the CS argument doesn't have the GPIO information in it. Instead, the user must
use "sf probe << 8>". For example, if bank 2 gpio 30 is used to force
cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must
type "sf probe 15872".This is inconsistent with the description of the sf probe command, and forces
the user to be aware of implementaiton details.Fix this by introducing a new board function: board_spi_cs_gpio(), which will
accept a naked CS value, and provide the driver with the relevant GPIO, if one
is necessary.Cc: Eric Nelson
Cc: Eric Benard
Cc: Fabio Estevam
Cc: Tim Harvey
Cc: Stefano Babic
Cc: Tom Rini
Cc: Marek Vasut
Reviewed-by: Marek Vasut
Signed-off-by: Nikita Kiryanov
Reviewed-by: Jagannadha Sutradharudu Teki
23 Sep, 2014
1 commit
22 Sep, 2014
1 commit
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- Use _defconfig instead of _config, but still _config is working.
- Corrected README.sandbox path in ./READMESigned-off-by: Jagannadha Sutradharudu Teki
Acked-by: Simon Glass
21 Sep, 2014
1 commit
19 Sep, 2014
1 commit
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Add NOR flash hardware init function, including SMC and PIO
configuration.Signed-off-by: Bo Shen
Reviewed-by: Andreas Bießmann
Signed-off-by: Andreas Bießmann
18 Sep, 2014
2 commits
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This patch implements a workaround to fix DDR3 memory issue.
The code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset.In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset.Signed-off-by: Murali Karicheri
Signed-off-by: Keegan Garcia
Signed-off-by: Ivan Khoronzhuk
17 Sep, 2014
2 commits
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Signed-off-by: Masahiro Yamada
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We do not have to distinguish CONFIG_TARGET_VEXPRESS_AEMV8A_SEMI
from CONFIG_TARGET_VEXPRESS_AEMV8A. Rename the former to the latter.Signed-off-by: Masahiro Yamada
Reviewed-by: Steve Rae
Cc: David Feng