19 Dec, 2014
4 commits
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We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.Currently the implementation is to call fsp_init() in the car_init().
We may move that call to cpu_init_f() in the future.Signed-off-by: Bin Meng
Acked-by: Simon Glass
17 Dec, 2014
1 commit
16 Dec, 2014
3 commits
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Add proper error checking into the PHY tuning patch. Make the PHY tunning only
happen in case the KSZ9021 PHY is enabled in config. Call the config callback
after the tuning finished.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Tom Rini
Cc: Pavel Machek -
A new interface is introduced to support generic board structure.
Converts it to use new interface.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun
14 Dec, 2014
2 commits
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Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.Signed-off-by: Bin Meng
Acked-by: Simon Glass
12 Dec, 2014
17 commits
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Conflicts:
board/freescale/mx6sxsabresd/mx6sxsabresd.cSigned-off-by: Tom Rini
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This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:- CONFIG_SYS_I2C_INIT_BOARD
- CONFIG_I2C_MULTI_BUS
- CONFIG_SYS_MAX_I2C_BUS
- CONFIG_SYS_I2C_SPEED
- CONFIG_SYS_I2CThis has been tested on:
- trimslice (no I2C)
- beaver
- Jetson-TK1It has not been tested on Tegra 114 as I don't have that board.
Acked-by: Heiko Schocher
Signed-off-by: Simon Glass -
Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but
it has a different panel, the sdcard cd and wp sense are flipped, and it has
a different revision of the AS3722 PMIC.This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA
Tegra K1, 2GB). The display is not currently supported, so it should
boot on other nyan-based Chromebooks also, but only the device tree for
nyan-big is provided here.The device tree file is from Linux but with features removed which are
unlikely to be supported in U-Boot soon (regulators, pinmux). Also the
addresses are updated to 32-bit.Signed-off-by: Allen Martin
Signed-off-by: Simon Glass
(rebase, change to 'nyan-big', fix pinmux that resets nyan-big) -
Adjust the configuration to use the driver model version of the pl01x
serial driver. Add the required platform data.Signed-off-by: Simon Glass
Tested-by: Stephen Warren -
LS1 has 4 SMMUs for address translation of the masters. All the
SMMUs' stream IDs are 8-bit. The address translation depends on the
stream ID of the incoming transaction.
Each master has unique stream ID assigned to it and is configurable
through SCFG registers. The stream ID for the masters is identical
and share the same register field of STREAM ID registers.Signed-off-by: Xiubo Li
Reviewed-by: York Sun -
The Central Security Unit (CSU) allows secure world software to
change the default access control policies of peripherals/bus
slaves, determining which bus masters may access them. This
allows peripherals to be separated into distinct security domains.
Combined with SMMU configuration of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.For now we configure all the peripheral access permissions as R/W.
Signed-off-by: Xiubo Li
Reviewed-by: York Sun -
With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun -
The Freescale LS1021AQDS share some pins, so Add the hwconfig option
that allows the user to choose which the function he wants.The main pin mux IP is:
eSDHC, SAI, IIC2, RGMII, CAN, SAI.Signed-off-by: Yuan Yao
Reviewed-by: York Sun -
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Alison Wang
Reviewed-by: York Sun -
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.Signed-off-by: Alison Wang
Reviewed-by: York Sun -
This patch adds SD boot support for LS1021ATWR board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.Signed-off-by: Chen Lu
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Reviewed-by: York Sun -
This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Reviewed-by: York Sun -
Through adding CONFIG_QIXIS_I2C_ACCESS macro,
QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used
for both i2c and ifc access to QIXIS FPGA. This is
more convenient for coding.Signed-off-by: Jason Jin
Signed-off-by: Alison Wang
Reviewed-by: York Sun -
When resuming from deep sleep, the I2C channel may not be
in the default channel. So, switch to the default channel
before accessing DDR SPD.Signed-off-by: Chenhui Zhao
Reviewed-by: York Sun -
The patch changes PCIe dts node status to 'disabled' if the
corresponding controller is disabled according to serdes protocol.Signed-off-by: Minghuan Lian
Reviewed-by: York Sun
10 Dec, 2014
7 commits
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Alt board has been connected to eMMC of 8GB to MMC port.
This enables MMC port and MMC command.Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu -
Lager board has been connected to eMMC of 8GB to MMC1 port.
This enables MMC1 port and MMC command.Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu -
Signed-off-by: Vikas Manocha
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Signed-off-by: Vikas Manocha
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stv0991 architecture support added. It contains the support for
following blocks
- Timer
- uartSigned-off-by: Vikas Manocha
[trini: Add arch/arm/cpu/armv7/Makefile hunk]
Signed-off-by: Tom Rini
09 Dec, 2014
2 commits
08 Dec, 2014
3 commits
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This board sprinkles #ifdef(CONFIG_HERMES) over various global files
such as include/common.h, common/board_r.c, common/cmd_bdinfo.c.
Let's zap such an ill-behaved board.It has not been converted to generic board yet and mpc8xx is old
enough.Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denk
Acked-by: Wolfgang Denk -
The U-Boot port runs on a variety of RPi models, not just the B. So,
rename the port to something slightly more generic.Signed-off-by: Stephen Warren
Reviewed-by: Simon Glass
Tested-by: Simon Glass -
Detect the board revision early during boot, and print the decoded
model name.Eventually, this information can be used for tasks such as:
- Allowing/preventing USB device mode; some models have a USB device on-
board so only host mode makes sense. Others connect the SoC directly
to the USB connector, so device-mode might make sense.
- The on-board USB hub/Ethernet requires different GPIOs to enable it,
although luckily the default appears to be fine so far.
- The compute module contains an on-board eMMC device, so we could store
the environment there. Other models use an SD card and so don't support
saving the environment (unless we store it in a file on the FAT boot
partition...)Set $fdtfile based on this information. At present, the mainline Linux
kernel doesn't contain a separate DTB for most models, but I hope that
will change soon.Signed-off-by: Stephen Warren
Reviewed-by: Simon Glass
Tested-by: Simon Glass
06 Dec, 2014
1 commit
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Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5
hardware.Signed-off-by: Dinh Nguyen
Cc: Vince Bridgers
Cc: Pavel Machek
Cc: Marek Vasut
Cc: Tom Rini
Cc: Albert Aribaud
Cc: Wolfgang Denk
