26 Apr, 2014

3 commits


24 Apr, 2014

3 commits


23 Apr, 2014

15 commits

  • Add support of 2 stage NAND/SD boot loader using SPL framework.
    PBL initialise the internal SRAM and copy SPL, this further
    initialise DDR using SPD and environment and copy u-boot from
    NAND/SD to DDR, finally SPL transfer control to u-boot.
    NOR uses CS1 instead of CS2 when NAND boot, fix it.

    Signed-off-by: Shaohui Xie
    Reviewed-by: York Sun

    Shaohui Xie
     
  • Updated the RCW for rev2.0 which uses new frequency settings as below:

    Clock Configuration:
    CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz,
    CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz,
    CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667MHz,
    CCB:733.333 MHz,
    DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz
    FMAN1: 733.333 MHz
    FMAN2: 733.333 MHz
    QMAN: 366.667 MHz
    PME: 533.333 MHz

    Remove workaround of IFC bus speed and SERDES A-006031 of rev1.0.

    Signed-off-by: Shaohui Xie
    Reviewed-by: York Sun

    Shaohui Xie
     
  • - update readme.
    - add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315
    ucode from NOR/NAND/SPI/SD/REMOTE.
    - update cpld vbank with SW3[5:7]=000 as default vbank0 instead of
    previous SW3[5:7]=111 as default vbank.
    - fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2.

    Signed-off-by: Shengzhou Liu
    Reviewed-by: York Sun

    Shengzhou Liu
     
  • Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
    PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
    SPL further initializes DDR using SPD and environment and copy
    u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control
    to u-boot.

    Signed-off-by: Shengzhou Liu
    Reviewed-by: York Sun

    Shengzhou Liu
     
  • Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
    PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
    SPL further initializes DDR using SPD and environment and copy
    u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers
    control to u-boot.

    Signed-off-by: Shengzhou Liu
    [York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH]
    Reviewed-by: York Sun

    Shengzhou Liu
     
  • There should be a break for case PHY_INTERFACE_MODE_SGMII, otherwise it
    will fall into case PHY_INTERFACE_MODE_RGMII.

    Signed-off-by: Shaohui Xie
    Reviewed-by: York Sun

    Shaohui Xie
     
  • Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
    here, PBL initialise the internal SRAM and copy SPL(160KB). This further
    initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
    Finally SPL transer control to u-boot.

    Initialise/create followings required for SPL framework
    - Add spl.c which defines board_init_f, board_init_r
    - update tlb and ddr accordingly

    Signed-off-by: Prabhakar Kushwaha
    Reviewed-by: York Sun

    Prabhakar Kushwaha
     
  • Add support of 2 stage NAND boot loader using SPL framework.
    here, PBL initialise the internal SRAM and copy SPL(160KB). This further
    initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
    Finally SPL transer control to u-boot.

    Initialise/create followings required for SPL framework
    - Add spl.c which defines board_init_f, board_init_r
    - update tlb and ddr accordingly

    Signed-off-by: Prabhakar Kushwaha
    Reviewed-by: York Sun

    Prabhakar Kushwaha
     
  • Add u-qe support for t1040qds

    Signed-off-by: Zhao Qiang
    Reviewed-by: York Sun

    Zhao Qiang
     
  • Add deep sleep support on T104xRDB platforms.

    Signed-off-by: Tang Yuantian
    Reviewed-by: York Sun

    Tang Yuantian
     
  • Add deep sleep support on T1040QDS platform.

    Signed-off-by: Tang Yuantian
    Reviewed-by: York Sun

    Tang Yuantian
     
  • T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.

    This support of CPLD includes
    - files and register defintion
    - Commands to swtich alternate bank and default bank

    Signed-off-by: Prabhakar Kushwaha
    Reviewed-by: York Sun

    Prabhakar Kushwaha
     
  • T1040QDS_D4 is a variant of T1040QDS, with additional circuit to support
    DDR4 memory. Tested with MTA9ASF51272AZ-2G1AYESZG.

    Signed-off-by: York Sun

    York Sun
     
  • The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher
    than 2.5 MHZ. It violates the IEEE specs.

    So Slow MDC clock to comply IEEE specs

    Signed-off-by: Prabhakar Kushwaha
    Reviewed-by: York Sun

    Prabhakar Kushwaha
     
  • For KVM we have a special PV machine type called "ppce500". This machine
    is inspired by the MPC8544DS board, but implements a lot less features
    than that one.

    It also provides more PCI slots and is supposed to be enumerated by
    device tree only.

    This patch adds support for the generic ppce500 machine and tries to
    rely solely on device tree for device enumeration.

    Signed-off-by: Alexander Graf
    Acked-by: Scott Wood
    Reviewed-by: York Sun

    Alexander Graf
     

20 Apr, 2014

1 commit


18 Apr, 2014

18 commits