07 Jan, 2016
1 commit
14 Nov, 2015
1 commit
02 Sep, 2015
3 commits
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All the rtc_only related functions are not needed for the second stage
of the bootloader hence pushing all the code under LOWLEVEL_INIT macro.This fixes compile time warning when built with am335x_evm_defconfig.
Signed-off-by: Keerthy -
If EMIF is idle for certain amount of DDR cycles, EMIF will put the
DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register
is programmed. And also before entering suspend-resume ddr needs to
be put in self-refresh. Linux kernel does not program this register
before entering suspend and relies on u-boot setting.
So configuring it in u-boot.Signed-off-by: Nishanth Menon
Signed-off-by: Lokesh Vutla -
On DRA7, refresh ctrl shadow should be updated with
the final value.Signed-off-by: Lokesh Vutla
28 Aug, 2015
1 commit
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clrsetbits_le32/clrbits_le32 takes mask of the bits as input that
are needed to be set/clear. But emif driver passes the shift of the bits.
Fixing it here.Reported-by: Mark Mckeown
Signed-off-by: Lokesh Vutla
21 Aug, 2015
3 commits
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DRA72x processor variants are single core and it does not export ACP[1].
Hence, we have no source for generating an external snoop requests which
appear to be key to the deadlock in DRA72x design.Since we build the same image for DRA74x and DRA72x platforms, lets
runtime detect and disable the workaround (in favor of performance) on
DRA72x platforms.[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html
Suggested-by: Richard Woodruff
Suggested-by: Brad Griffis
Reviewed-by: Brad Griffis
Signed-off-by: Nishanth Menon
(cherry picked from commit 095a5ef88e08c3df0f273c20a39cb921900cfae6)
Signed-off-by: Dan Murphy -
Implement logic for ACR(Auxiliary Control Register) configuration using
ROM Code smc service.Suggested-by: Richard Woodruff
Suggested-by: Brad Griffis
Reviewed-by: Brad Griffis
Signed-off-by: Nishanth Menon
(cherry picked from commit 1bbb556a6a5c0f44d2da32700fce4d279c851e9f)
Signed-off-by: Dan Murphy -
Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
that "A livelock can occur in the L2 cache arbitration that might
prevent a snoop from completing. Under certain conditions this can
cause the system to deadlock. "Recommended workaround is as follows:
Do both of the following:1) Do not use the write-back no-allocate memory type.
2) Do not issue write-back cacheable stores at any time when the cache
is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
is implementation defined whether cacheable stores update the cache when
the cache is disabled it is not expected that any portable code will
execute cacheable stores when the cache is disabled.For implementations of Cortex-A15 configured without the “L2 arbitration
register slice” option (typically one or two core systems), you must
also do the following:3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111
So, we provide an option to disable write streaming on OMAP5 and DRA7.
It is a rare condition to occur and may be enabled selectively based
on platform acceptance of risk.Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
is set to 0.Note: certain unicore SoCs *might* not have REVIDR[3] not set, but
might not meet the condition for the erratum to occur when they donot
have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
Extensions). Such SoCs will need the work around handled in the SoC
specific manner, since there is no ARM generic manner to detect such
configurations.Based on ARM errata Document revision 18.0 (22 Nov 2013)
Suggested-by: Richard Woodruff
Suggested-by: Brad Griffis
Reviewed-by: Brad Griffis
Signed-off-by: Nishanth Menon
(cherry picked from commit a615d0be6a73fc48a22e5662608260fe9b9149ff)
Signed-off-by: Dan Murphy
13 Aug, 2015
2 commits
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DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet
provided IODELAY values for standard RGMII phys do not work.Silicon Revision(SR) 2.0 provides an alternative bit configuration
that allows us to do a "gross adjustment" to launch the data off a
different internal clock edge. Manual IO Delay overrides are still
necessary to fine tune the clock-to-data delays. This is a necessary
workaround for the quirky ethernet Phy we have on the platform.NOTE: SMA registers are spare "kitchen sink" registers that does
contain bits for other workaround as necessary as well. Hence the
control for the same is introduced in a generic SoC specific, board
generic location.Signed-off-by: Nishanth Menon
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For am43xx_rtconly_evm_defconfig, the bootloader indicates support for
RTC-Only modes by writing a magic number into RTC scratch register
which kernel PM code will then clear and then write back again if
RTC-Only mode entry is desired. If no PM code is loaded in the kernel,
this magic number will not get cleared and then be detected again
by the bootloader on a warm reboot, indicating an RTC+DDR resume event
and causing the bootloader to attempt to jump to the resume address in
RTC scratch register 0, which is invalid.Add a check to prevent jumping to address 0 if the scratch register is
not properly programmed, otherwise warm reboot will not work on am437x
if no PM is loaded in the kernel.Signed-off-by: Dave Gerlach
12 Aug, 2015
2 commits
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ARM supported speeds and init value of core_pll for SDP1200
are programmed wrong as part for the device speed cleanups.
Fixing it here.Signed-off-by: Lokesh Vutla
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On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov "
and based on the previous work done by "Hao Zhang "Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov
Tested-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla
07 Aug, 2015
7 commits
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Add in code to initialize the DWC3 gadget controller so that we can do
RNDIS in SPL on these platforms.Signed-off-by: Tom Rini
Signed-off-by: Kishon Vijay Abraham I -
Now that we have separate function to enable USB clocks, remove
enabling USB clocks from enable_basic_clocks(). Now board_usb_init()
should take care to invoke enable_usb_clocks() for enabling
USB clocks.Signed-off-by: Kishon Vijay Abraham I
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Added functions to enable and disable USB clocks which can be invoked
during USB init and USB exit respectively.Cc: Roger Quadros
Cc: Tero Kristo
Cc: Nishanth Menon
Signed-off-by: Kishon Vijay Abraham I -
Added functions to enable and disable USB clocks which can be invoked
during USB init and USB exit respectively.Cc: Roger Quadros
Cc: Tero Kristo
Cc: Nishanth Menon
Signed-off-by: Kishon Vijay Abraham I -
Implemented board_usb_init(), board_usb_cleanup() and
usb_gadget_handle_interrupts() in omap5 board file that
can be invoked by various gadget drivers.Signed-off-by: Kishon Vijay Abraham I
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Implemented board_usb_init(), board_usb_cleanup() and
usb_gadget_handle_interrupts() in beagle_x15 board file that
can be invoked by various gadget drivers.Signed-off-by: Kishon Vijay Abraham I
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Enabled clocks for the second dwc3 controller and second USB PHY present in
DRA7.Signed-off-by: Kishon Vijay Abraham I
05 Aug, 2015
20 commits
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Add MMC support for k2g
Signed-off-by: Roger Quadros
Signed-off-by: Lokesh Vutla
Tested-by: Mugunthan V N -
In K2G, Ethernet doesn't support SGMII instead it support RGMII,
adding support to the driver to connect to RGMII phy.Signed-off-by: Vitaly Andrianov
Signed-off-by: Mugunthan V N
Signed-off-by: Lokesh Vutla -
Phy mode is a board property and it can be different between
multiple board and ports, so it should not be hardcoded in
driver to one specific mode. So adding a field in eth_priv_t
structure to pass phy mode to driver.Signed-off-by: Mugunthan V N
Signed-off-by: Lokesh Vutla -
update K2G nav rx queue number
Signed-off-by: Vitaly Andrianov
Signed-off-by: Mugunthan V N
Signed-off-by: Lokesh Vutla -
Coreect base addresses for SPI, Queue Manager, Ethernet, GPIO,
and MSMC segments.Signed-off-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla -
Add api for configuring pin mux.
Signed-off-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla -
Add ddr3 related info
Signed-off-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla -
Add psc information for k2g
Signed-off-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla -
Add clock information for Galileo
Signed-off-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla
Signed-off-by: Mugunthan V N -
Add pll data for k2g
Signed-off-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla -
Add Kconfig support
Signed-off-by: Lokesh Vutla
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Adding CPU detection support for Keystone2 Galileo.
Signed-off-by: Lokesh Vutla
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Since all the clocks are defined common, and has the same logic to get
the frequencies, use a common definition for for clk_get_rate().Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla -
Remove unused external clocks and make a common definition
for all keystone platforms.Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla -
This is just a cosmetic change that makes
the calling of pll init code looks much cleaner.Reviewed-by: Tom Rini
Reviewed-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla -
Register Base addresses are same for PLLs in all
keystone platforms. If a PLL is not available, the corresponding
register addresses are marked as reserved.
Hence use a common definition.Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla -
Use common devspeed and armspeed definitions.
Also fix reading efuse bootrom register.Reviewed-by: Tom Rini
Reviewed-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla -
There are two types of PLL for all keystone platforms:
Main PLL, Secondary PLL. Instead of duplicating the same definition
for each secondary PLL, have a common function which does
initialization for both PLLs. And also add proper register
definitions.Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla -
Add print_cpuinfo() function and enable
CONFIG_DISPLAY_CPUINFO for keystone platforms,
so that cpu info can be displayed during boot.Reviewed-by: Tom Rini
Reviewed-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla -
Add proper register definition for JTAG ID and
cleanup cpu_is_* functions.Reviewed-by: Tom Rini
Reviewed-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla