10 Dec, 2021
1 commit
21 Jul, 2021
1 commit
19 Jul, 2021
1 commit
23 Feb, 2021
1 commit
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* origin/imx_v2020.04:
MLK-25310 imx8m: ddr: Disable CA VREF Training for LPDDR4
21 Feb, 2021
1 commit
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Users reported LPDDR4 MR12 value is set to 0 during PHY training,
not the value from FSP timing structure, which cause compliance test failed.
The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
but not set in 1D. According to PHY training application node,
to enable the feature both 1D and 2D need set this field to 1,
otherwise the training result will be incorrect.
The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
MR12 value from message block (FSP structure). So update the LPDDR4
scripts of all mscale to clear CATrainOpt[0].Signed-off-by: Ye Li
Reviewed-by: Jacky Bai
(cherry picked from commit 2c98fb859258478e0f8bb8df980a96edff19d359)
05 Feb, 2021
6 commits
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* origin/imx_v2020.04:
MLK-25291-3 imx8mq_evk: Applying default LPDDR4 script for B2
MLK-25291-2 misc: ocotp: Update OCOTP driver for iMX8MQ B2
MLK-25291-1 iMX8MQ: Recognize the B2 revision -
Both i.MX8MQ B1 and B2 should use default LPDDR4 script, while B0
has another dedicated script.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 2beb72ddfd5416be7d8fa6e9fb36b1e29a0f0cb7) -
* origin/ls_v2020.04: (8 commits)
configs: ls208xa: Enable GIC_V3_ITS config
configs: ls1028a: Enable GIC_V3_ITS config
configs: ls1088a: Enable GIC_V3_ITS config
arm64: layerscape: Move GIC RD tables initialization to CPU setup function
fsl-layerscape: Kconfig: Select RESV_RAM config if GIC_V3_ITS is enabled
... -
Move GIC redistributor tables initialization to CPU setup function.
This patch introduces a GIC redistributor tables init function, and
moves the function of reserving memory for GIC redistributor tables
to soc.c and adds a argument for the memory size to reserve, BTW
rename the function so that it is more readable.Signed-off-by: Hou Zhiqiang
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As the lower 16bit of the redistributor pending table is reserved
for describing the memory attributes, we must give a 64KB aligned
address to the GIC LPI initialization function.Signed-off-by: Hou Zhiqiang
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Program the GIC redistributor tables only when succeeded to reserve memory
for them, otherwise kernel will lose the chance to program them using
allocated memory.Signed-off-by: Hou Zhiqiang
28 Jan, 2021
1 commit
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* origin/imx_v2020.04:
MA-18635 Android: eliminate build warnings
MA-18634-2 Android: sync config change
MA-18634-1 Android: refine config dependency
17 Jan, 2021
1 commit
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Refine the dependency of some configs to make it
easier to add/modify android config files.Test: builds.
Change-Id: Iccb044dadc7ce1e0b839bf83e2e9157e718f286c
Signed-off-by: Ji Luo
(cherry picked from commit 86f4f99a367bbc0ef99d4ab2a0b4078babfbfbd2)
13 Jan, 2021
2 commits
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* origin/ls_v2020.04:
armv8: ls1028a: fix stream id allocation
configs: ls1088aqds: add COMMON_ENV to fix distroboot
board: fsl: ls2088ardb: Program GIC LPI configuration table -
Program GIC LPI configuration table:
1. Redistributor PROCBASER configuration table (which is common for all
redistributors)2. Redistributor pending table (PENDBASER), for all the available
redistributors.3.Reserve DDR memory region used for GIC LPI configuration table.
Signed-off-by: Nikhil Gupta
08 Jan, 2021
1 commit
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VDD SOC normal run changed to 0.85V
LPDDR4 freq0 change from 4000MTS to 2400MTSChange-Id: I69676ea5b582a817fb3c367bd861db96ba647540
(cherry picked from commit 1205f1edfaed1383181d4d52344cc55e5e92a351)
20 Nov, 2020
1 commit
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* origin/dn_uboot: (14 commits)
Revert "mmc: move mmc_power_cycle() after controller initialization"
Revert "mmc: rework mmc_set_initial_state"
board: freescale: vid.c: add parantheses to fix build warning
net: pfe_eth: read PFE ESBC header flash with spi_flash_read API
lx2160a: Fix address for secure boot headers
...
19 Nov, 2020
3 commits
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To avoid u-boot MMU table overlap M4 RPMSG vring buffer, reserve
the top 1MB DDR.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit e00224b10c9ce10c76fa9ba452d88565bee7024a) -
To avoid u-boot MMU table overlap M4 RPMSG vring buffer. Reserve
the top 1MB DDR when bootaux is enabled.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 44cf26781117c484e5f7e46fe6008c0b31c297e4) -
When booting with M4 RPMSG demo in u-boot, the M4 will use top 1MB
DDR for RPMSG vring buffer. This overlaps with u-boot MMU table and
modifies some MMU entries.
On mx7dsabresd, this cause u-boot failed to access LCDIF registers
due to the wrong MMU entries.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 8a03d17c92cc04765c6b93f716ea081486fd15f0)
09 Nov, 2020
6 commits
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Since iMX8MP LPDDR4 EVK uses OD for VDD_SOC, so we can set GIC clock
to 500Mhz to align with kernel. For DDR4 EVK, uses default 400Mhz for
ND VDD_SOC.
Move the codes from SOC codes to board level to match with voltage
setting.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit ba50b01b74873cbddaeba61f69e7763a8ba63227) -
Because DDR4 runs at 3200MTS, this speed does not require to use overdrive
voltage for VDD_SOC, so set VDD_SOC to nominal 0.85v on DDR4 EVK.
The VDD_ARM was set to 0.95v to avoid timing risk from SOC to ARM when
VDD_SOC is 0.95v, set it back to 0.85v as well.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 5d556b8e214739deb5c3c71efa2ea8fc28f2a643) -
Add prarantheses to fix build warning as follows,
if (!strict_strtoul(argv[1], 10, &override))
^~
board/freescale/common/vid.c:976:3: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the if
if (ret < 0)Signed-off-by: Biwen Li
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Read PFE ESBC header flash with spi_flash_read API
- logs as follows,
Net: SF: Detected s25fs512s with page size 256 Bytes, erase size 256
KiB, total 64 MiB
"Synchronous Abort" handler, esr 0x96000210
elr: 000000008206db44 lr : 0000000082004ea0 (reloc)
elr: 00000000b7ba6b44 lr : 00000000b7b3dea0
x0 : 00000000b79407e8 x1 : 0000000040640000
x2 : 0000000000000050 x3 : 0000000000000000
x4 : 000000000000000a x5 : 0000000000000050
x6 : 0000000000000366 x7 : 00000000b7942308
x8 : 00000000b76407c0 x9 : 0000000000000008
x10: 0000000000000044 x11: 00000000b7634d1c
x12: 000000000000004f x13: 0000000000000044
x14: 00000000b7634d98 x15: 00000000b76407c0
x16: 0000000000000000 x17: 0000000000000000
x18: 00000000b7636dd8 x19: 0000000000000000
x20: 00000000b79407d0 x21: 00000000b79407e8
x22: 0000000040640000 x23: 00000000b7634e58
x24: 0000000000000000 x25: 0000000003800000
x26: 00000000b7bdd000 x27: 0000000000000000
x28: 0000000000000000 x29: 00000000b7634d10Code: d2800003 eb03005f 54000101 d65f03c0 (f8636826)
Resetting CPU ...Signed-off-by: Biwen Li
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Make sure are RGMII internal delay modes are covered.
Signed-off-by: Madalin Bucur
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Signed-off-by: Madalin Bucur
06 Nov, 2020
1 commit
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Use a dedicated defconfig for LCDIF splash screen to resolve conflict.
Update board codes to add relevant configs and control mux for LCDIF pins.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit b561b31da6aeafd189f0fa29d8d6b8c3fe28d1c9)
05 Nov, 2020
1 commit
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Update address length argument
Signed-off-by: Biwen Li
03 Nov, 2020
1 commit
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Add check for return value of adjust_vdd()
Signed-off-by: Priyanka Singh
30 Oct, 2020
3 commits
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Signed-off-by: Ye Li
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Use more safer refresh time value for 6GB LPDDR4 on this EVK board.
Update the parameters for every frequency point.Signed-off-by: Ye Li
Reviewed-by: Jacky Bai
(cherry picked from commit f0f496abb5d7bef031603d1c3ab5387facead209) -
1. align ddr4 Q0S settings to lpddr4
2. adjust PERFHPR1, PERFLPR1, PERFWR1 to reduce HPR,LPR, W
starving time to avoid display underrunSigned-off-by: Jian Li
Reviewed-by: Ye Li
(cherry picked from commit f0905916886bd45d1dc5d55b25839106457124f5)
29 Oct, 2020
2 commits
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Initialize variable 'i2caddress' in adjust_vdd() to zero
Signed-off-by: Priyanka Singh
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Enable writes to all commands for LTC3882
Signed-off-by: Biwen Li
19 Oct, 2020
6 commits
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Conflicts:
arch/arm/cpu/armv8/Kconfig
drivers/pci/pcie_layerscape_fixup.c
drivers/video/imx/Makefile
drivers/video/nxp/Kconfig
drivers/video/nxp/Makefile
drivers/video/nxp/hdp/Makefile
drivers/video/nxp/hdp/test_base_sw.cSigned-off-by: Ye Li
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Initialize variable 'i2caddress' in print_vdd() to zero
Signed-off-by: Priyanka Singh
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mux changes in board file to enable lpuart1 and macro
define for lpuart1 used for mux changes in board configuation
register 13Signed-off-by: Vabhav Sharma
Signed-off-by: Yuantian Tang -
Rename old LPDDR4 EVK to EVK-QCA board which uses QCA wifi and BD71847
pmic, assign dedicated u-boot DTS and defconfig for this board, So we
can drop it easily in future.Set default EVK configuration for new LPDDR4 EVK which uses NXP PCA9540A
PMIC and NXP AW-CM358SM WIFI module.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit c8f5dbeecd7d7fb620b7652166378246c7ce8470) -
This board uses 4GB DDR4 and replace emmc and flexspi to a raw NAND
socket. Add the support for this board, including SD boot, NAND boot,
and inline ECC (top 1/8 DDR used for ecc).Signed-off-by: Ye Li
Acked-by: Peng Fan
(cherry picked from commit 9b47aaef967bb7655312895c133e64e32e8f5b87) -
This commit does some clean-up to guard the codes/configs with
correct configs, so we can enable/disable the feature without
modifying the codes.Test: builds and boots on imx8qm.
Signed-off-by: Ji Luo
Change-Id: Ic4cf4d9f47bd5a4317b2621a5378cb4b192e52fb
(cherry picked from commit 2c2363e47b858bd178c44869328eca211b2c3f62)
