11 Mar, 2014
1 commit
-
Signed-off-by: Ian Campbell
Acked-by: Rob Herring
10 Mar, 2014
1 commit
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CONFIG_SYS_HZ must be always 1000, but M5271EVB.h defines it
as 1000000 and idmr.h defines it as (50000000 / 64).When compiling these two boards, a warning message is displayed:
time.c:14:2: warning: #warning "CONFIG_SYS_HZ must be 1000
and should not be defined by platforms" [-Wcpp]There are no board maintainers for them so this commit just
deletes them.Signed-off-by: Masahiro Yamada
Cc: Jason Jin
08 Mar, 2014
10 commits
-
Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
two Chip selects.
-Update board_specific_parameters udimm structure with settings
derived via calibration.
-Update ddr_raw_timing sructure corresponding to DIMM.
-Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
but on T104xRDB, on setting this , DDR instability is observed.
Board-level debugging is in progress.Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.Signed-off-by: Priyanka Jain
Signed-off-by: York Sun -
T1040 has internal display interface unit (DIU) for driving video.
T1040QDS supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoderChrontel, CH7301C encoder which is I2C programmable is used as
HDMI connector on T1040QDS.
This patch add support to
-enable Video interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on boardSigned-off-by: Priyanka Jain
Reviewed-by: York Sun -
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
It works in two mode: standalone mode and PCIe endpoint mode.T2080PCIe-RDB Feature Overview
------------------------------
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
DDR Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LP devices
- 72bit 4GB DDR3-LP SODIMM in slot
Ethernet interfaces:
- Two 10M/100M/1G RGMII ports on-board
- Two 10Gbps SFP+ ports on-board
- Two 10Gbps Base-T ports on-board
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes 16 lanes configuration:
- SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
- SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
- SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
- SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
- SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
- SerDes-2 Lane G-H: to SATA1 & SATA2
IFC/Local Bus:
- NOR: 128MB 16-bit NOR flash
- NAND: 512MB 8-bit NAND flash
- CPLD: for system controlling with programable header on-board
eSPI:
- 64MB N25Q512 SPI flash
USB:
- Two USB2.0 ports with internal PHY (both Type-A)
PCIe:
- One PCIe x4 gold-finger
- One PCIe x4 connector
- One PCIe x2 end-point device (C293 Crypto co-processor)
SATA:
- Two SATA 2.0 ports on-board
SDHC:
- support a TF-card on-board
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial portsSigned-off-by: Shengzhou Liu
Reviewed-by: York Sun -
Change QIXIS timing parameter CONFIG_SYS_CS3_FTIM2 to 8 from 0.
Fix EMI2 for t2080qds, which was caused by adding t2081qds.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384)
and at cold temperatures(A006475), workaround recalibrate the
PLLs with some SerDes configurationBoth these errata are only applicable for b4 rev1.
So, make workaround for these errata conditional,
depending upon soc version.Signed-off-by: Shaveta Leekha
Reviewed-by: York Sun -
Change setting of SerDes2 refclk2 to have the default value as it is
coming on board that is 156.25MHz, for XFI to work.
Also change PLL_NUM variable to the one defined in config_mpc85xx.h
for B4860 and B4420.Signed-off-by: Shaveta Leekha
Reviewed-by: York Sun -
On B4860 and B4420, some serdes protocols can be used with LC VCO as
well as Ring VCO options.Addded Alternate options with LC VCO for such protocols.
For example protocol 0x2a on srds 1 becomes 0x29 if it is LC VCO.The alternate option has the same functionality as the original option;
the only difference being LC VCO rather than Ring VCO.Signed-off-by: Poonam Aggrwal
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
1) SerDes2 Refclks have been set properly to make
PCIe SATA to work as it work on SerDes refclk of 100MHz
2) Mask the SerDes's device reset request before changing
the Refclks for SerDes1 and SerDes2 for PLL locks to
happen properly, device reset request bit unmasked
after SerDes refclks configurationSigned-off-by: Shaveta Leekha
Reviewed-by: York Sun -
1) Add new SerDes1 protocols having Aurora in them
2) Add VSC cross point connections for Aurora to work with
CPRI and SGMIIs
3) Configure VSC crossbar switch to connect SerDes1
lanes to aurora on board, by checking SerDes1 protocols
4) SerDes1 Refclks have been set properly to make
Aurora, CPRI and SGMIIs to work together properlySigned-off-by: Shaveta Leekha
Reviewed-by: York Sun
07 Mar, 2014
4 commits
-
Before this commit, CONFIG_MPC8260 and CONFIG_8260
were used mixed-up.All boards with mpc8260 cpu defined both of them:
- CONFIG_MPC8260 was defined in board config headers
and include/common.h
- CONFIG_8260 was defined arch/powerpc/cpu/mpc8260/config.mkWe do not need to have both of them.
This commit keeps only CONFIG_MPC8260.This commit does:
- Delete CONFIG_8260 and CONFIG_MPC8260 definition
in config headers and include/common.h
- Rename CONFIG_8260 to CONFIG_MPC8260
in arch/powerpc/cpu/mpc8260/config.mk.
- Rename #ifdef CONFIG_8260 to #ifdef CONFIG_MPC8260Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denk -
Many (but not all) of Blackfin boards give -O2 option
to compile under lib/ directory.
That means lib/ should be speed-optimized,
whereas other parts should be size-optimized.We want to keep the same behavior,
but do not want to parse board/*/config.mk again and again.
We've got no choice but to invent a new method.CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED, if it is enabled,
gives -O2 flag only for building under lib/ directory.Dirty codes which I had marked as "FIX ME"
in board/${BOARD}/config.mk have been deleted.
Instead, CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED has been
defined in include/configs/${BOARD}.h.Signed-off-by: Masahiro Yamada
Cc: Sonic Zhang -
As ppc4xx currently only supports the deprecated nand_spl infrastructure
and nobody seems to have time / resources to port this over to the newer
SPL infrastructure, lets remove NAND booting completely.This should not affect the "normal", non NAND-booting ppc4xx platforms
that are currently supported.Signed-off-by: Stefan Roese
Cc: Wolfgang Denk
Cc: Tirumala Marri
Cc: Matthias Fuchs
Cc: Masahiro Yamada
Cc: Tom Rini
Tested-by: Matthias Fuchs -
config.tmp is never generated
Signed-off-by: Masahiro Yamada
Cc: Michal Simek
Acked-by: Michal Simek
05 Mar, 2014
8 commits
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omap_gpmc.h is a generic header used by OMAP NAND driver for all TI platfoms.
Hence this file should be present in generic folder instead of architecture
specific include folder.
Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5Signed-off-by: Pekon Gupta
-
There are no source files in board/synopsys/arcangel4/
directory.Signed-off-by: Masahiro Yamada
Cc: Alexey Brodkin -
config.tmp is not there.
Signed-off-by: Masahiro Yamada
-
Ignore
- board/cray/L1/bootscript.{c|image}
- board/matrix_vision/mvblm7/bootscript.img
- board/maxtir_vision/mvsmr/bootscript.imgSigned-off-by: Masahiro Yamada
Cc: Andre Schwarz -
The same outputs are generated with or without -I$(TOPDIR)/board.
I cannot understand why it is necessary. Remove.Signed-off-by: Masahiro Yamada
Cc: Daniel Hellstrom -
Convert sandbox over to use driver model GPIOs.
Signed-off-by: Simon Glass
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Copied from Linux sources "include/linux/sizes.h" commit
413541dd66d51f791a0b169d9b9014e4f56be13cSigned-off-by: Alexey Brodkin
Cc: Vineet Gupta
Cc: Tom Rini
Cc: Stefan Roese
Cc: Albert Aribaud
Acked-by: Tom Rini
Acked-by: Stefan Roese
[trini: Add bcm Kona platforms to the patch]
Signed-off-by: Tom Rini
04 Mar, 2014
3 commits
-
board/sheldon/simpc8313/config.mk is used only for nand_spl.
So it should go into nand_spl/board/sheldon/simpc8313/.Signed-off-by: Masahiro Yamada
-
Read ram size directly from DTB.
Signed-off-by: Michal Simek
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NAND boot mode on AM335x EVM has been verified, and steps
to use it has been documented and update in this READMESigned-off-by: Pekon Gupta
Acked-by: Peter Korsgaard
Acked-by: Tom Rini
27 Feb, 2014
4 commits
-
Conflicts:
arch/arm/cpu/armv7/config.mk
board/ti/am43xx/mux.c
include/configs/am43xx_evm.hSigned-off-by: Tom Rini
-
Remove the last uses of symbol offsets in ARM U-Boot.
Remove some needless uses of _TEXT_BASE.
Remove all _TEXT_BASE definitions.Signed-off-by: Albert ARIBAUD
-
This prevents references to _end from generating absolute
relocation records.This change is binary invariant for ARM targets.
Signed-off-by: Albert ARIBAUD
-
Newly added cm_t335 was missed in commit 47ed5dd0 which
made ARM targets produce full ELF files. Fix its linker
script.This change is binary-invariant when only .dynsym, .dynstr,
.dynamic, .plt, .interp and .gun sections are declared.Sections .hash, .got.plt, .dynbss and .ARM.exidx are also
declared so that their (unused) content is moved out of the
u-boot binary.Signed-off-by: Albert ARIBAUD
26 Feb, 2014
2 commits
-
With this, fixup a trivial build error of get_effective_memsize needing
to be updated in the new board/freescale/p1010rdb/spl.cSigned-off-by: Tom Rini
-
Rename OBJCFLAGS to OBJCOPYFLAGS beforehand to use
"cmd_objcopy" in scripts/Makefile.lib in an upcoming commit.Signed-off-by: Masahiro Yamada
25 Feb, 2014
2 commits
-
In the previous patches, we introduced the SPL/TPL fraamework.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.Signed-off-by: Ying Zhang
Reviewed-by: York Sun -
T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
- Two on-board 10M/100M/1G bps RGMII ports
- Two 10Gbps XFI with on-board SFP+ cage
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
- Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
- 8 lanes up to 10.3125GHz
- Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
- 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
- Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
voltage translators
- I2C:
- Four I2C controllers.
- UART:
- Dual 4-pins UART serial portsSigned-off-by: Shengzhou Liu
Reviewed-by: York Sun
24 Feb, 2014
2 commits
-
HOSTCFLAGS_autoconf.mk.dep was added by commit 422322f
but it has never been used.Cc: Vadim Bendebury
Cc: Simon Glass
Signed-off-by: Masahiro Yamada
23 Feb, 2014
1 commit
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Add support for the bcm28155_ap reference board.
Signed-off-by: Darwin Rambo
Reviewed-by: Steve Rae
Reviewed-by: Tim Kryger
22 Feb, 2014
2 commits
-
New hardware version cannot recognize the SD-Card
because the SYS_NRESWARM, set as GPIO, does not
guarantee the required reset time.
Change the pin function back to enable the
SYS_NRESWARM signal driven by the SOC.Signed-off-by: Stefano Babic
-
Schematic indicates GPIO5_7 is to be used for VTT regulator control
rather than GPIO0_21 so modify enable_vtt_regulator to reflect this.
Without this some boards will experience DDR3 corruption and fail to
boot.Signed-off-by: Dave Gerlach
[trini: Rework patch against mainline]
Signed-off-by: Tom Rini
