06 Oct, 2014
12 commits
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The timer reload value is a property of the timer hardware and there
is no reason for this to be configurable. Place this into the timer
driver just like on the other hardware.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Dinh Nguyen
Acked-by: Pavel Machek -
Add the missing pieces from the reference clock code from Altera. This
puts the code on par with the Altera U-Boot fork for all but the SDRAM
self-refresh bits, which are not part of this patch.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Clean up the clock code definitions so they are aligned with mainline
standards. There are no functional changes in this patch.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Pull out functions to read frequency of Main clock VCO and
PLL clock VCO as the code is duplicated multiple times.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Dinh Nguyen
Acked-by: Pavel Machek -
Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel MachekV2: Fixed the L4 MP clock divider and synced the clock code with latest
rocketboards codebase (thanks Dinh for pointing this out) -
The inlining is done by GCC when needed, there is no need to do it
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint for the compiler. Scrub this hint.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Dinh Nguyen
Acked-by: Pavel Machek -
The bit definitions for clock manager are complete chaos. Implement
some basic logical order into them.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Clean up the system manager register definition and add the missing
register definitions in place.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel MachekV2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h
Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default) -
Sort the list of functional block addresses and fix indentation.
No functional change.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek
Acked-by: Chin Liang See -
Add base addresses for all subsystems as documented in the
Cyclone V HPS documentation.Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Chin Liang See -
Add configuration for the write-allocate mode of L1 D-Cache on ARM.
This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA .Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek
26 Sep, 2014
4 commits
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With some versions of gcc (that we know of 4.6.3 and 4.8.2 are affected)
it is necessary to specify --bss-plt to get the final blrl in the
_GOT2_TABLE_. Without this the last symbol does not get it's address
relocated. For the P2041RDB board this ended up being
NetArpWaitTimerStart which caused the ARP packets to timeout
immediately.Signed-off-by: Joakim Tjernlund
Signed-off-by: Chris Packham
Acked-by: Joakim Tjernlund
Acked-by: Scott Wood
Reviewed-by: York Sun -
LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.Signed-off-by: York Sun
CC: Alison Wang
25 Sep, 2014
8 commits
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Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table is used for each core. Spin table
and the boot page is reserved in device tree so OS won't overwrite.Signed-off-by: York Sun
Signed-off-by: Arnab Basu -
DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).Signed-off-by: York Sun
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U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.Signed-off-by: York Sun
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This commit moves:
CONFIG_OF_CONTROL
CONFIG_OF_SEPARATE
CONFIG_OF_EMBED
CONFIG_OF_HOSTFILEBecause these options are currently not supported for SPL,
the "Device Tree Control" menu does not appear in the SPL
configuration.Note:
zynq-common.h should be adjusted so as not to change the
default value of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME.Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
Cc: Stephen Warren
Cc: Minkyu Kang
Acked-by: Michal Simek -
The macro MIN, MAX is defined as the aliase of min, max,
respectively.Signed-off-by: Masahiro Yamada
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Each CPU of PowerPC has its default linker script under the CPU
directory, except mpc8xx.Every mpc8xx board has its own linker script under the board
directory, resulting in lots of duplication of linker scripts.I notice eight mpc8xx boards have the same linker script.
We can decrease the number of linker scripts by putting a single
default linker script, arch/powerpc/cpu/mpc8xx/u-boot.lds.Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denk
Acked-by: Stefan Roese -
"0x00" is a valid serdes protocol for QorIQ parts, and can not be
used to test whether the serdes is enabled or disabled.Signed-off-by: Ebony Zhu
Reviewed-by: York Sun -
Fix following issues in USB device-tree fixup:
- returns when either dr_mode or phy_type not defined.
This was terminating fix-up when only either property
was defined in hwconfig string
- updates dr_mode_type or dr_phy_type with junk value when
their index is -1. Now these are updated only when their
respective index is pointing to relevant types
in modes[] and phys[] array
- dr_mode_type and dr_phy_type were not NULL for
each controllerSigned-off-by: Ramneek Mehresh
Reviewed-by: York Sun
24 Sep, 2014
1 commit
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Signed-off-by: Stefan Roese
Tested-by: Luka Perkov
Reviewed-by: Jagannadha Sutradharudu Teki
21 Sep, 2014
1 commit
19 Sep, 2014
3 commits
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Using CPU_HAS_PCR micro to present the SoC has pcr
(peripheral control register).Signed-off-by: Bo Shen
Signed-off-by: Andreas Bießmann -
When use pcr (peripheral control register), then we won't need
to care about the peripheral ID.Signed-off-by: Bo Shen
Signed-off-by: Andreas Bießmann -
Signed-off-by: Bo Shen
Reviewed-by: Andreas Bießmann
Signed-off-by: Andreas Bießmann
18 Sep, 2014
3 commits
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This patch implements a workaround to fix DDR3 memory issue.
The code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset.In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset.Signed-off-by: Murali Karicheri
Signed-off-by: Keegan Garcia
Signed-off-by: Ivan Khoronzhuk
17 Sep, 2014
3 commits
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At the high level, the problem is that we set gd multiple times (and
still do, even after the commit we're reverting). We set important
parts of gd to the copy which is not above stack but rather in the data
section. For the release, we're going to revert this change and for the
next release we shall correct things to only, really, set gd once to an
appropriate location and ensure that comments about it are correct too.This reverts commit f0c3a6c4ad09210d5d4aeafe87685ee75e5683d6.
Acked-by: Albert Aribaud
Signed-off-by: Tom Rini -
Signed-off-by: Masahiro Yamada
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We do not have to distinguish CONFIG_TARGET_VEXPRESS_AEMV8A_SEMI
from CONFIG_TARGET_VEXPRESS_AEMV8A. Rename the former to the latter.Signed-off-by: Masahiro Yamada
Reviewed-by: Steve Rae
Cc: David Feng
14 Sep, 2014
3 commits
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Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME}
are specified in arch/Kconfig.We can delete the ones in arch and board Kconfig files.
This commit can be easily reproduced by the following command:
find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e '
/config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ {
N
s/\n[[:space:]]*string//
}
'Signed-off-by: Masahiro Yamada
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This commit adds the type definitions (+ help messages) of
CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME} to arch/Kconfig,
which would save lots of type defs for taget boards.
(See also the next commit.)Signed-off-by: Masahiro Yamada
12 Sep, 2014
2 commits
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The boards using CONFIG_SYS_DV_NOR_BOOT_CFG (i.e. calimain,
da850evm_direct_nor and enbw_cmc) had the _start symbol defined after
the CONFIG_SYS_DV_NOR_BOOT_CFG word rather than before it in
arch/arm/lib/vectors.S. Because of that, if by lack of luck
'gd->mon_len = (ulong)&__bss_end - (ulong)_start' (see setup_mon_len())
was a multiple of 4 kiB (see reserve_uboot()), then the last BSS word
overlapped the first word of the following reserved RAM area (or went
beyond the top of RAM without such an area) after relocation because
__image_copy_start did not match _start (see relocate_code()).This was broken by commit 41623c9 'arm: move exception handling out of
start.S files', which defined _start twice (before and after the
CONFIG_SYS_DV_NOR_BOOT_CFG word), then by commit 0a26e1d 'arm: fix a
double-definition error of _start symbol', which kept the definition of
the _start symbol after the CONFIG_SYS_DV_NOR_BOOT_CFG word. This new
commit fixes this issue by restoring the original behavior, i.e. by
defining the _start symbol before the CONFIG_SYS_DV_NOR_BOOT_CFG word.Signed-off-by: Benoît Thébaudeau
Cc: Albert Aribaud
Cc: Manfred Rudigier
Cc: Christian Riesch
Cc: Sudhakar Rajashekhara
Cc: Heiko Schocher
