14 Jan, 2014
8 commits
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For standalone images, bootm had a special case where the OS boot function
was NULL but did actually exist. It was just called manually.This was removed by commit 35fc84fa which checks for the non-existence of
this function before the special case is examined.There is no obvious reason why standalone is handled with a special case.
Adjust the code so that standalone has a normal OS boot function. We still
need a special case for when the function returns, but at least we can
avoid the main problem.This is intended to fix the reported:
ERROR: booting os 'U-Boot' (17) is not supported
but needs testing.
Signed-off-by: Simon Glass
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Issues:
- reading i2c data by passing u16 pointer causes errors in read data.
- max17042 status register fields have not only Power On Reset meaning
so using proper mask is required.Changes:
- read i2c data to type u32 instead of u16 - avoids buffer overflow
- compare FG status register using mask not just one bit value
- add checking return value to functions fg read/write
- add model lock and model check count
- add debug msgSigned-off-by: Przemyslaw Marczak
Cc: Lukasz Majewski
Cc: Minkyu Kang -
Otherwise, when booting VxWorks kernel, the incorrect message will
be seen:ARM Unknown OS Kernel Image (uncompressed)
Signed-off-by: Miao Yan
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Compiling of full list of commands does not advance the counter,
so it always results in an empty list.
This seems to be (inadvertently?) introduced by commit
6c7c946cadfafdea80eb930e3181085b907a0362.Signed-off-by: Andrew Gabbasov
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Variable uncompressedSize references the space available, while outSizeFull is
the actual expected uncompressed size. Using the wrong value causes LzmaDecode
to return SZ_ERROR_INPUT_EOF. Problem was introduced in commit afca294. While
at it add additional debug message.Signed-off-by: Antonios Vamporakis
CC: Kees Cook
CC: Simon Glass
CC: Daniel Schwierzeck
CC: Luka Perkov -
Signed-off-by: Tom Rini
13 Jan, 2014
17 commits
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Access the OneNAND 1KiB window on the VPAC270 as an SRAM instead of accessing
it as a burst-RAM. This fixes a problem where the board failed to reboot
sometimes as the CPU couldn't start executing from the OneNAND 1KiB window.Signed-off-by: Marek Vasut
Cc: Albert Aribaud
Cc: Tom Rini -
The OneNAND SPL used on PXA is slightly obscure. Due to the OneNAND limitation,
where we have only the first 1KiB of the OneNAND available upon power-up as a
memory-mapped area, from which the CPU starts executing, we place only the most
essential code into this first 1KiB . This code copies the rest of the SPL into
SRAM and jumps to it. This code is stored in section .text.0 .The rest of the SPL is stored in section .text.1 . When running the OBJCOPY on
the SPL, it will preserve only .text section, but the .text.0 and .text.1 are
stripped away from the result, thus making the SPL binary empty. The patch adds
additional -j parameters to the OBJCOPY for PXA during the SPL build, which will
preserve the .text.0 and .text.1 sections.Moreover, this patch also adds missing functions into the .text.0 section, since
otherwise the PXA270 with 1KiB-window OneNAND won't be able to boot.Signed-off-by: Marek Vasut
Cc: Albert Aribaud
Cc: Tom Rini -
Before this change ums mode can not be entered when device
was using the same usb port for usb/uart communication.
Switching USB cable from UART to USB always causes ums exit.Signed-off-by: Przemyslaw Marczak
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Arndale board has AX88760, which is USB 2.0 Hub & USB 2.0 Ethernet Combo
controller, connected to HSIC Phy of USB host controller via USB3503 hub.This patch uses board specific board_usb_init function to perform reset
sequence for USB3503 hub and enables the relevant config options for
network to work.Signed-off-by: Inderpal Singh
Signed-off-by: Chander Kashyap -
The controller has 3 ports. The port0 is for USB 2.0 Phy, port1 and port2
are for HSIC phys. The usb 2.0 phy is already being setup. This patch
sets up the hsic phys.Signed-off-by: Inderpal Singh
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The fifo size of ep0 is 64 bytes, and if the packet size grater than
64 bytes, the driver would have to fill up the fifo multiple times,
and before filling up the fifo, the driver should make sure the fifo
is empty by checking fifo empty indication.However there is a hardware bug that the fifo empty indication is
somehow a bit earlier than fifo reset. So if I don't add an extra
delay here, the data might be corrupted. (i.e., 1 byte missing)After a couple of tests, it truns out that 1 usec is good enough.
This workaround should be applied to all hardware revisions.
Signed-off-by: Kuo-Jung Su
CC: Marek Vasut -
Since hardware revision 1.11.0, the following interrupt status
registers are now W1C (i.e., write 1 clear):1. Interrupt Source Group 0 Register (0x144) (EP0 Abort: BIT5)
2. Interrupt Source Group 2 Register (0x14C) (All bits)And before revision 1.11.0, these registers are all R/W.
Which means software must write a 0 to clear the status.Signed-off-by: Kuo-Jung Su
CC: Marek Vasut -
The array reserved as a placeholder in the structure ipu_idmac
should contain 44 32bit unsigned integer entries instead of 45
ones, because the placeholder is located bewteen the register
IDMAC_SC_CORD1 and the register IDMAC_CH_BUSY_1 with the address
offsets of 0x804c and 0x8100 respectively.Reported-by: Robin Gong
Acked-by: Robin Gong
Cc: Stefano Babic
Signed-off-by: Liu Ying -
The array reserved1 as a placeholder in the structure ipu_cm
should contain 4 32bit unsigned integer entries instead of 16
ones, because the placeholder is located bewteen the register
IPU_CH_DB_MODE_SEL_1 and the register IPU_ALT_CH_DB_MODE_SEL_0
with the address offsets of 0x154 and 0x168 respectively.Reported-by: Robin Gong
Acked-by: Robin Gong
Cc: Stefano Babic
Signed-off-by: Liu Ying -
Remove the flag SECT_4K for device N25Q128 as the 4K-byte
sub sector erase granularity is available only for top/bottom
8 sectors in some of the N25Q128 chips.Signed-off-by: Siva Durga Prasad Paladugu
Reviewed-by: Jagannadha Sutradharudu Teki -
Updated current SPI subsyetem status.
Signed-off-by: Jagannadha Sutradharudu Teki
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This config will use for defining greater than single flash support.
currently - DUAL_STACKED and DUAL_PARALLEL.Signed-off-by: Jagannadha Sutradharudu Teki
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This patch added support for accessing dual memories in
parallel connection with single chipselect line from controller.For more info - see doc/SPI/README.dual-flash
Signed-off-by: Jagannadha Sutradharudu Teki
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This patch added support for accessing dual memories in
stacked connection with single chipselect line from controller.For more info - see doc/SPI/README.dual-flash
Signed-off-by: Jagannadha Sutradharudu Teki
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Unified the bar code from read_ops into a spi_flash_bar()
Signed-off-by: Jagannadha Sutradharudu Teki
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- comment typo's
- func args have a proper namesSigned-off-by: Jagannadha Sutradharudu Teki
11 Jan, 2014
14 commits
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QEB code comprises of couple of flash register read/write operations,
this patch moved flash register operations on to sf_opSigned-off-by: Jagannadha Sutradharudu Teki
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Added macronix flash quad read/write commands support and
it's up to the respective controller driver usecase to
configure the respective commands by defining SPI RX/TX
operation modes from include/spi.h on the driver.Signed-off-by: Jagannadha Sutradharudu Teki
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This patch adds set QEB support for macronix flash devices
which are trying to program/read quad operations.Signed-off-by: Jagannadha Sutradharudu Teki
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Discovered the read dummy_byte based on the
configured read command.Signed-off-by: Jagannadha Sutradharudu Teki
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This patch adds support QUAD_IO_FAST read command.
Signed-off-by: Jagannadha Sutradharudu Teki
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Moved the flash params table from sf_probe.c and
placed on to sf_params.c, hence flash params file will
alter based on new addons.Signed-off-by: Jagannadha Sutradharudu Teki
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This patch enabled RD_FULL and WR_QPP for supported flashes
in micron, winbond and spansion.Remaining parts will be add in future patches.
Signed-off-by: Jagannadha Sutradharudu Teki
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This patch provides support to set the quad enable bit on flash.
quad enable bit needs to set before performing any quad IO
operations on respective SPI flashes.Currently added set quad enable bit for winbond and spansion flash
devices. stmicro flash doesn't require to set as qeb is volatile.
remaining flash devices support will add in future patches.Signed-off-by: Jagannadha Sutradharudu Teki
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This patch provides support to program a flash config register.
Configuration register contains the control bits used to configure
the different configurations and security features of a device.Signed-off-by: Jagannadha Sutradharudu Teki
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This patch add quad commands support like
- QUAD_PAGE_PROGRAM => for write program
- QUAD_OUTPUT_FAST ->> for read programSigned-off-by: Jagannadha Sutradharudu Teki
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Current sf uses FAST_READ command, this patch adds support to
use the different/extended read command.This implementation will determine the fastest command by taking
the supported commands from the flash and the controller, controller
is always been a priority.Signed-off-by: Jagannadha Sutradharudu Teki
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We have a sh_spi_clear_bit() function, there's no reason not to use it.
Signed-off-by: Axel Lin
Acked-by: Nobuhiro Iwamatsu
Reviewed-by: Jagannadha Sutradharudu Teki -
Add map_sysmem() calls so that this test works correctly on sandbox.
Signed-off-by: Simon Glass
Reviewed-by: Hung-ying Tyan
Reviewed-by: Jagannadha Sutradharudu Teki -
The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF. However This
patch implements only the SPI mode.NOTE:
The DMA and CS/Clock control logic has been altered
since hardware revision 1.19.0. So this patch
would first detects the revision id of the underlying
chip, and then switch to the corresponding software
control routines.Signed-off-by: Kuo-Jung Su
Signed-off-by: Jagannadha Sutradharudu Teki
CC: Tom Rini
10 Jan, 2014
1 commit
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Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.Conflicts:
include/configs/exynos5250-dt.hSigned-off-by: Tom Rini