10 Oct, 2014
9 commits
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Signed-off-by: David Müller
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Signed-off-by: David Müller
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These boards have been orphaned for more than 6 months.
Signed-off-by: Masahiro Yamada
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These boards have been orphaned for more than 6 months.
Signed-off-by: Masahiro Yamada
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This board has been orphaned for more than 6 months.
It is the last board defining CONFIG_APM821XX.
The code inside #ifdef CONFIG_APM821XX should be removed too.Signed-off-by: Masahiro Yamada
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This board has been orphaned for more than 6 months.
Signed-off-by: Masahiro Yamada
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These boards have been orphaned for more than 6 months.
Signed-off-by: Masahiro Yamada
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On OMAP platforms, SATA controller provides the SCSI subsystem
so implement scsi_init().Get rid of the unnecessary sata_init() call from dra7xx-evm
and omap5-uevm board files.Signed-off-by: Roger Quadros
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Commit 12cc54376768461533b55ada1b0b6d4979f40579 'omap3: overo: Select
fdtfile for expansion board' wrongly missed the operator in the fdtfile
test. Update the test to only overwrite an empty fdtfile environment
variable.Signed-off-by: Stefan Herbrechtsmeier
07 Oct, 2014
3 commits
06 Oct, 2014
13 commits
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Enable and use the CONFIG_CMD_FS_GENERIC to avoid hard-coding the
filesystem type into the environment.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Split the SoCFPGA configuration into SoC-specific part which is
common for all boards (socfpga_cyclone5_common.h) and a board
specific part. There is currently only one board, which is the
generic SoCFPGA board (socfpga_cyclone5.h), but there are more
to come.This is necessary due to various features of the boards, which
unfortunatelly cannot be autodetected.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Reorganize and cleanup the configuration file for SoCFPGA. There
is no functional change after this cleanup. This was necessary,
since the file was a wild mess and it was impossible to make sense
of it's content, let alone change something without breaking some
other thing. This patch puts the contents on par with regular U-Boot
standards.Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER
and CONFIG_USE_IRQ, which is undefined by default. Finally, do
logical reordering of the defines in the file so it's much more
readable. The reordering was also necessary for the splitting
as the initial one was messy.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek -
Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit.
Enable the bootz command as zImage is used instead uImage.Signed-off-by: Chin Liang See
Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc: Marek Vasut
Cc: Tom Rini
Cc: Albert Aribaud
Cc: Wolfgang Denk
Acked-by: Pavel Machek -
Enable the DesignWare MMC controller driver support
for SOCFPGA Cyclone5 dev kitSigned-off-by: Chin Liang See
Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc: Marek Vasut
Cc: Tom Rini
Cc: Albert Aribaud
Cc: Wolfgang Denk
Acked-by: Pavel Machek -
Enable the PL310 L2 cache controller support for the SoCFPGA.
With the cache related issues resolved, this is safe to be done.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
The Cortex-A9 has 32-byte long L1 cachelines. Define this value.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
The timer reload value is a property of the timer hardware and there
is no reason for this to be configurable. Place this into the timer
driver just like on the other hardware.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Dinh Nguyen
Acked-by: Pavel Machek -
Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel MachekV2: Fixed the L4 MP clock divider and synced the clock code with latest
rocketboards codebase (thanks Dinh for pointing this out) -
Remove this symbol from configs, since it's unused.
Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Cc: Joe Hershberger
Acked-by: Chin Liang See -
Besides converting the LS-XHL and LS-CHLv2 to generic board, fix a typo
which accidentally reverted the bootsource to 'hdd' although the default
bootsource should be 'legacy'.Cc: Tom Rini
Cc: Prafulla Wadaskar
Signed-off-by: Michael Walle
Signed-off-by: Prafulla Wadaskar -
Siemens boards are now using DFU in fullspeed only. For
this CONFIG_USB_GADGET_DUALSPEED is undefined.Signed-off-by: Heiko Schocher
Cc: Tom Rini
Cc: Lukasz Majewski
Cc: Marek Vasut
Cc: Liu Bin
Cc: Lukas Stockmann
05 Oct, 2014
1 commit
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These are used by Panasonic UniPhier SoC family.
Signed-off-by: Masahiro Yamada
01 Oct, 2014
5 commits
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This patch add HUSH command parser
Signed-off-by: Gerald Kerma
Changes in v1:
- add HUSH command parser
Signed-off-by: Prafulla Wadaskar -
This patch redefine MTDPARTS
Signed-off-by: Gerald Kerma
Changes in v1:
- redefine MTDPARTS
Signed-off-by: Prafulla Wadaskar -
This patch add MTDIDS and MTDPARTS defaults settings to sheevaplug
Signed-off-by: Gerald Kerma
Changes in v1:
- add MTDIDS and MTDPARTS default to sheevaplug
Signed-off-by: Prafulla Wadaskar -
This patch add MVSATA driver to sheevaplug
Signed-off-by: Gerald Kerma
Changes in v1:
- add MVSATA driver to sheevaplug
- enable ext4 FS support
Signed-off-by: Prafulla Wadaskar -
This patch move the environment offset in sheevaplug.
The size of the u-boot binary is become too big.
Fix saving environments was result of corrupting the u-boot.Signed-off-by: Gerald Kerma
Changes in v2:
- patch descriptionChanges in v1:
- fix sheevaplug environment offset
Signed-off-by: Prafulla Wadaskar
27 Sep, 2014
2 commits
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Sandbox may as well support everything. This increases the amount of code
that is built/tested by sandbox, and also provides access to all the
supported SPI flash devices.Signed-off-by: Simon Glass
Reviewed-by: Jagannadha Sutradharudu Teki
26 Sep, 2014
3 commits
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LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.Signed-off-by: York Sun
CC: Alison Wang
25 Sep, 2014
4 commits
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When booting with SP, RCW resides at the beginning of IFC NOR flash.
Signed-off-by: York Sun
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Spin table is at the very beginning of boot code. Each core has an individual
release address within the spin table, the ft_cpu_setup fn updates the
"cpu-release-addr" property of each cpu node with the corresponding release
address.Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.
Signed-off-by: York Sun
Signed-off-by: Arnab Basu -
DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).Signed-off-by: York Sun
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Add support of NOR and NAND flash for simulator target.
Here
IFC - CS0: NOR flash
IFC - CS1: NAND flashSigned-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun
