Eric Lee / smarc-uboot

06 Jun, 2016

2 commits

  • df0052575   MLK-12883 usb: limit USB_MAX_XFER_BLK to 256 ... Browse Code »
    8

    For Some USB mass storage devices, such as:
    "
    - Kingston DataTraveler 2.0 001D7D06CF09B04199C7B3EA
    - Class: (from Interface) Mass Storage
    - PacketSize: 64 Configurations: 1
    - Vendor: 0x0930 Product 0x6545 Version 1.16
    "
    When `usb read 0x80000000 0 0x2000`, we met
    "EHCI timed out on TD - token=0x80008d80".

    The devices does not support scsi VPD page, we are not able
    to get the maximum transfer length for READ(10)/WRITE(10).

    So we limit this to 256 blocks as READ(6).

    Signed-off-by: Peng Fan

    Peng Fan
     
  • b4bc642c6   MLK-12884 mx7dsabresd: Fix LCD_PWR_EN output setting ... Browse Code »

    LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect
    D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3
    is actually 1.2V.

    Signed-off-by: Ye Li
    (cherry picked from commit 28eb616b6c49de492cc0cdb3ad5b618bed77960f)

    Ye Li
     

03 Jun, 2016

1 commit

  • 139a6f95b   MLK-12852 ocotp: mxc: mx6ull: fix GP3/GP4 prog ... Browse Code »

    Bank 7 and Bank 8 only supports 4 words each. 'bank << 3 | word'
    is not correct when program bank 8, since ocotp controller actully
    use word index.

    For example: fuse prog 8 3 1; The word index is (8 << 3 | 3) --> 67.
    But actully it should be (7 << 3 | 7) ---> 63.
    So fix it.

    Signed-off-by: Peng Fan

    Peng Fan
     

31 May, 2016

1 commit

24 May, 2016

1 commit

23 May, 2016

2 commits

16 May, 2016

3 commits

  • 68fbb20f0   MLK-12798 imx6ull: fix snvs tamper pin usage ... Browse Code »

    SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
    not in IOMUXC, so correct the related registers' offset.

    Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
    them from iomuxc pins.

    Define CONFIG_IOMUX_LPSR for mx6ull_ddr3_arm2 board to enable
    using these pins.

    Signed-off-by: Peng Fan

    Peng Fan
     
  • 1f0bb3940   MLK-12800 imx: mx7dsabresd: support revC ... Browse Code »

    Add revC board support.

    Signed-off-by: Peng Fan

    Peng Fan
     
  • 7f00c72e1   MLK-12791 mx6qpsabresd: Change ENET TXCLK clock from PLL ... Browse Code »
    6

    In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY,
    While kernel uses the clock from internal PLL by setting GPR5 bit 9.
    When doing warm reset in kernel, the GPR regigster is not reset, so
    the clock source still is the PLL. This causes ENET in u-boot can't work.

    In this patch, we change the u-boot to use internal PLL to align with
    kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset.

    Signed-off-by: Ye Li

    Ye Li
     

11 May, 2016

1 commit

10 May, 2016

1 commit

  • ee6717667   imx: iomux-v3: fix UART input selects ... Browse Code »

    Several UART input selects are missing. The fourth input select
    for UART2_TX_DATA_ALT0 is actually also missing in the documentation.
    (at least in Rev. B of the i.MX 7Dual Reference Manual). However,
    when looking at the tables of other input selects, it is very natural
    that there must be an input select for the UART2_TX_DATA_ALT0 pad.
    The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and
    it was required to set that particular input select register to get a
    working UART2.

    From https://www.mail-archive.com/u-boot@lists.denx.de/msg211942.html

    Signed-off-by: Peng Fan

    Stefan Agner
     

09 May, 2016

5 commits

07 May, 2016

1 commit

  • 489929be0   MLK-12693-2 nand: mxs: correct bitflip for erased NAND page ... Browse Code »
    25

    This patch is a porting of
    http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38
    "
    i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
    bitflip number for erased NAND page. So for these two platform, set the
    erase threshold to gf/2 and if bitflip detected, GPMI driver will
    correct the data to all 0xFF.

    Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
    with the one for i.MX6QP.
    "

    In this patch, i.MX6UL is added and threshold changed to use ecc_strength.

    Signed-off-by: Peng Fan

    Peng Fan
     

06 May, 2016

3 commits

  • ceb324a29   MLK-12693-1 nand: mxs: fix the bitflips for erased page when uncorrectable error ... Browse Code »
    25

    This patch is porting from linux:
    http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=3d42fcece496224fde59f9343763fb2dfc5b0768

    "
    We may meet the bitflips in reading an erased page(contains all 0xFF),
    this may causes the UBIFS corrupt, please see the log from Elie:

    -----------------------------------------------------------------
    [ 3.831323] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
    [ 3.845026] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
    [ 3.858710] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
    [ 3.872408] UBI error: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read 16384 bytes
    ...
    [ 4.011529] UBIFS error (pid 36): ubifs_recover_leb: corrupt empty space LEB 27:237568, corruption starts at 9815
    [ 4.021897] UBIFS error (pid 36): ubifs_scanned_corruption: corruption at LEB 27:247383
    [ 4.030000] UBIFS error (pid 36): ubifs_scanned_corruption: first 6569 bytes from LEB 27:247383
    -----------------------------------------------------------------

    This patch does a check for the uncorrectable failure in the following steps:

    [0] set the threshold.
    The threshold is set based on the truth:
    "A single 0 bit will lead to gf_len(13 or 14) bits 0 after the BCH
    do the ECC."

    For the sake of safe, we will set the threshold with half the gf_len, and
    do not make it bigger the ECC strength.

    [1] count the bitflips of the current ECC chunk, assume it is N.

    [2] if the (N

    Peng Fan
     
  • 8183b6020   imx: imx7d: fix ahb clock mux 1 ... Browse Code »

    The clock parent of the AHB root clock when using mux option 1
    is the SYS PLL 270MHz clock. This is specified in Table 5-11
    Clock Root Table of the i.MX 7Dual Applications Processor
    Reference Manual.

    While it could be a documentation error, the 270MHz parent is
    also mentioned in the boot ROM configuration in Table 6-28: The
    clock is by default at 135MHz due to a POST_PODF value of 1
    (=> divider of 2).

    Signed-off-by: Stefan Agner

    Stefan Agner
     
  • 22f6c4b15   MLK-12723 imx: Change the env offset on NAND to 60M ... Browse Code »
    6

    Current environment offset on NAND is 37MB, this will cause a alignment
    issue when erasing if nand erase block is 2MB. The saveenv is failed.

    => saveenv
    Saving Environment to NAND...
    Erasing NAND...
    Attempt to erase non block-aligned data

    Since the max erase block we supported is 4MB, adjust the env offset to 60MB,
    where is the last 4MB in 64MB reserved area for boot.

    Signed-off-by: Ye Li

    Ye Li
     

04 May, 2016

2 commits

  • 8a7d61d07   MLK-12629-2: i.MX6QP: update plugin ... Browse Code »

    For i.MX6QP, the QoS settings is different from others. Align with DCD.

    Signed-off-by: Peng Fan

    Peng Fan
     
  • 4329120dc   MLK-12629-1: imx6: cache: disable L2 before touching Auxiliary Control Register ... Browse Code »

    According PL310 TRM, Auxiliary Control Register
    "
    The register must be written to using a secure access, and it can be
    read using either a secure or a NS access. If you write to this register
    with a NS access, it results in a write response with a DECERR response,
    and the register is not updated. Writing to this register with the L2
    cache enabled, that is, bit[0] of L2 Control Register set to 1,
    results in a SLVERR.
    "

    So If L2 cache is already enabled, chaning value of ACR will cause SLVERR,
    uboot hangs.

    In some cases, such as plugin, L2 Cache enabled bit is not cleared,
    then "Set bit 22 in the auxiliary control register" cause uboot hangs.

    Signed-off-by: Peng Fan

    Peng Fan
     

03 May, 2016

2 commits

29 Apr, 2016

4 commits

  • 0a4b78f3b   MLK-12736 mx6ulevk: Delete obsoleted android build target ... Browse Code »

    The build target mx6ul_14x14_evk_android_defconfig is obsoleted.
    It is replaced by mx6ul_14x14_evk_brillo_defconfig. So remove this old file.

    Signed-off-by: Ye Li

    Ye Li
     
  • f521de2c5   MLK-12735 mx6qpsabresd: Update DDR script to version 1.14 ... Browse Code »
    6

    DDR script file:
    arik_r2_sdb_ddr3_528_1.14.inc

    Compass link:
    http://compass.freescale.net/livelink/livelink?func=ll&objid=235302593&objAction=browse&sort=name&viewType=1

    Update:
    setmem /32 0x020e0534 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 (SDQS0_B_TRIM=01, SDQS0_TRIM=10)
    setmem /32 0x020e0538 = 0x00008000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 (SDQS1_B_TRIM=00, SDQS1_TRIM=00)
    setmem /32 0x020e053C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 (SDQS2_B_TRIM=01, SDQS2_TRIM=10)
    setmem /32 0x020e0540 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 (SDQS3_B_TRIM=01, SDQS3_TRIM=10)
    setmem /32 0x020e0544 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 (SDQS4_B_TRIM=01, SDQS4_TRIM=10)
    setmem /32 0x020e0548 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 (SDQS5_B_TRIM=01, SDQS5_TRIM=10)
    setmem /32 0x020e054C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 (SDQS6_B_TRIM=01, SDQS6_TRIM=10)
    setmem /32 0x020e0550 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 (SDQS7_B_TRIM=01, SDQS7_TRIM=10)

    setmem /32 0x021b08c0 = 0x24912489 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
    setmem /32 0x021b48c0 = 0x24914452

    setmem /32 0x021b0018 = 0x00011740 // MMDC0_MDMISC, RALAT=0x5, WALAT=0x1

    Test:
    Passed stress memtester on one board.

    Signed-off-by: Ye Li
    (cherry picked from commit b7f43f47a78c9d0c14fe104daf22efab13709ab1)

    Ye Li
     
  • 69e4d3f02   MLK-12705-2 imx7d: add build target for TO1.1 ... Browse Code »

    Default build target supports TO1.0 and TO1.2,
    TO1.1 uses its own defconfig.

    Signed-off-by: Anson Huang

    Anson Huang
     
  • 2091a5fee   MLK-12705-1 ARM: imx: add support for i.MX7D TO1.2 ... Browse Code »

    i.MX7D TO1.2 uses same DDR script as TO1.0,
    TO1.1 uses dedicated DDR script.

    Signed-off-by: Anson Huang
    (cherry picked from commit 527d57e02b05eb0166dcaa1929e46dd2357a8720)

    Anson Huang
     

28 Apr, 2016

1 commit

22 Apr, 2016

1 commit

  • 519bc30d2   MLK-12694 mx6ullarm2: Remove the CD detection of SD2 ... Browse Code »

    Since the CD pin of SD2 is DNP on the mx6ull arm2 board, this will cause
    SD2 access problem even the card is inserted. Hard code the CD result to
    1 to assume the card is always on.
    The SD driver will return other errors if the card does not exist.

    Signed-off-by: Ye Li
    (cherry picked from commit 47efe2fda62297ab1da8594828cd7bd928ecbda7)

    Ye Li
     

21 Apr, 2016

4 commits

20 Apr, 2016

1 commit

  • 5c8c027bc   MLK-12677 mx6ullarm2: Update DDR script to version 2.1 ... Browse Code »

    File:
    IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.1.inc

    Changes:
    Change ZQ_OFFSET to the default value:00
    setmem /32 0x021B0890 = 0x00400000
    Change IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET.DDR_SEL to 11
    setmem /32 0x020E0288 = 0x000C0030
    Change duty cycle fine tune cell for SDCLK and SDQS
    setmem /32 0x021B08C0 = 0x00944009

    Test:
    One mx6ull ARM2 board passed memtest.

    Signed-off-by: Ye Li
    (cherry picked from commit 8128b2f3b419a1d15a0489a91e56a4ac82eaf0c4)

    Ye Li
     

15 Apr, 2016

1 commit

  • c5f3ebc2b   MLK-12658 imx: adjust POR_B setting on i.MX6ULL ... Browse Code »

    Adjust POR_B settings on i.MX6ULL according to design
    team's suggestion:

    2'b00 : always PUP100K
    2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL
    2'b10 : always disable PUP100K
    2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended setting

    Signed-off-by: Anson Huang

    Anson Huang
     

13 Apr, 2016

3 commits