05 Feb, 2021
1 commit
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i.MX8MQ B2 is using same value in OCOTP_READ_FUSE_DATA like B1, so
we have to check the ROM verision to distinguish the revision.As we have checked the B1 rev for sticky bits work around in
secure boot. So it won't apply on B2.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 1ac96bde4920fa3e2a3bb4a79b342ca4f5adb4a5)
16 Nov, 2020
1 commit
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There are 3 part numbers for 11x11 i.MX8MNano with different core number
configuration: UltraLite Quad/Dual/SoloComparing with i.MX8MN Lite parts, they have MIPI DSI disabled. So
checking the MIPI DSI disable fuse to recognize these parts.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 05af9ac08052c92d011908726534e227db3143c4)
26 Aug, 2020
2 commits
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8DXL A1 revision uses same id register value with revision B,
so A1 chip is recognized as RevB. Add new dummy chip revision for
8DXL A1 and A2 to distinguish with of RevB and RevCSigned-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 687f605630e0b87e963419aa59dec06d0f7b9cb1) -
Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so
update u-boot to remove decoding and support for those parts.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit ae3d51bd650bf4ef8e731c935c8f02c19d8f1df1)
16 Jun, 2020
1 commit
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iMX8MP has 6 fused parts in each qualification tier, with core, VPU,
ISP, NPU or DSP fused respectively.The configuration tables for enabled modules:
MIMX8ML8DVNLZAA Quad Core, VPU, NPU, ISP, DSP
MIMX8ML7DVNLZAA Quad Core, NPU, ISP
MIMX8ML6DVNLZAA Quad Core, VPU, ISP
MIMX8ML5DVNLZAA Quad Core, VPU
MIMX8ML4DVNLZAA Quad Lite
MIMX8ML3DVNLZAA Dual Core, VPU, NPU, ISP, DSPAdd the support in u-boot and update kernel DTS to disable nodes for
fused modulesSigned-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 9f8a807c5984b9d7859e6a70a2807843ab95b3f6)
06 May, 2020
5 commits
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Add soc id in cpu codes and conditionals.
Also add support for v2x container on 8DXL.Signed-off-by: Ye Li
Signed-off-by: Teo Hall
(cherry picked from commit 35691a6b85c3240b0e3b9f9a8da9fc6328bf92d8) -
Add REVC informaiton.
Signed-off-by: Frank Li
(cherry picked from commit c7231f2c7a5c1dc754b5fb9bf05941141877a0ec)
(cherry picked from commit 9a33170a4f4ff2ad2ab0d87e74e722a0e833abaa) -
According to datasheet, there are totally 6 variant parts for imx8mn:
Quad, Dual, Solo with core number changed.
QuadLite, DualLite, SoloLite with core number changed and GPU disabled.Add the support for these variant parts
1. Recognize the variant parts according to fuse
2. Power down disabled cores
3. Remove the cores node and disable GPU node from kernel DTB before
entering kernel.
4. Since the mscale dummy id has been used out, increase one more bit
(bit 8) for cpu id.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 144bd9ce223ead71e1726bea510242a3166f66ce)
(cherry picked from commit 380370b5460cb3f5284828fe0aabc7cca29c3bcd) -
iMX8MQ has two variant versions: iMX8MD and iMX8MQLite. Add dummy CPU ID
for these two, and check the fuses to get correct versions.Signed-off-by: Ye Li
(cherry picked from commit 58b77b541311d4b1d7db787cc769a7ad23ecbc79)
(cherry picked from commit a01c2144b5b97b62cb07be01487600116150af9d) -
Since commit 8891410c729b ("MLK-19848 mx6dq: Fix chip version issue for
rev1.3") it's not possible to call the HAB API functions on i.MX6DQ
SoC Rev 1.3:Authenticate image from DDR location 0x12000000...
undefined instruction
pc : [] lr : []
reloc pc : [] lr : []
sp : 8ef444a8 ip : 126e8068 fp : 8ff59aa8
r10: 8ffd51e4 r9 : 8ef50eb0 r8 : 006e8000
r7 : 00000000 r6 : 126ea01f r5 : 0000002b r4 : 126e8000
r3 : 412c00dd r2 : 00000001 r1 : 00000001 r0 : 00000063
Flags: nzCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...resetting ...
The hab.h code is defining the HAB API base address according to the
old SoC revision number, thus failing when calling the HAB API
authenticate_image() function.Fix this issue by using mx6dq rev 1.3 instead of mx6dq rev 1.5.
Signed-off-by: Breno Lima
Reviewed-by: Ye Li
(cherry picked from commit adc4d93e6e1726f111e86ca74fb76215215dbc86)
(cherry picked from commit a4300029173afb872b7e7e38d191ca5528da7fed)
08 Jan, 2020
1 commit
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Support get i.MX8MP cpu id and cpu type
Signed-off-by: Peng Fan
05 Nov, 2019
1 commit
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Add a dummy cpu type and support get_cpu_rev for i.MX8MN
Signed-off-by: Peng Fan
08 Oct, 2019
2 commits
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Add i.MX8MM cpu type and related helper functions
Signed-off-by: Peng Fan
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Add i.MX6ULZ cpu type and helper.
Signed-off-by: Peng Fan
Reviewed-by: Ye Li
Reviewed-by: Fabio Estevam
25 Apr, 2019
1 commit
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Add cpu type and Kconfig entry
Signed-off-by: Peng Fan
01 Jan, 2019
2 commits
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Rename mx8m,MX8M to imx8m,IMX8M
Signed-off-by: Peng Fan
Signed-off-by: Jon Nettleton -
Introduce CHIP_REV_2_1 macro.
Signed-off-by: Peng Fan
22 Oct, 2018
2 commits
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print_cpuinfo() in board init code requires uclass CPU driver,
add it to be able to display CPU info when CONFIG_DISPLAY_CPUINFO
option is enabled. CPU node in DT will have to include 'clocks'
and 'u-boot,dm-pre-reloc' properties for generic print_cpuinfo()
to work as expected. The driver outputs info for i.MX8QXP Rev A
and Rev B CPUs.Signed-off-by: Anatolij Gustschin
Cc: Stefano Babic
Reviewed-by: Peng Fan -
Add i.MX8 cpu type and is_imx8/is_imx8qxp help macros.
Signed-off-by: Peng Fan
Cc: Stefano Babic
07 May, 2018
1 commit
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.Signed-off-by: Tom Rini
04 Feb, 2018
1 commit
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Add i.MX8MQ SoC Revision
Add is_mx8m helper
The 7ULP is a dummy number, so use 0xEx.Signed-off-by: Peng Fan
Reviewed-by: Fabio Estevam
Cc: Stefano Babic
Reviewed-by: Stefano Babic
06 Jun, 2017
1 commit
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These declarations should not be in common.h. Move them to an
arch-specific header.Signed-off-by: Simon Glass
17 Mar, 2017
1 commit
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Implement soc level functions to get cpu rev, reset cause, enable cache,
etc. We will disable the wdog and init clocks in s_init at very early u-boot
phase.Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev
is hard coded to a fixed value. This may change in future.Reuse some code in imx-common.
Signed-off-by: Peng Fan
Signed-off-by: Ye Li
Cc: Stefano Babic
16 Dec, 2016
1 commit
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Add i.MX6SLL cpu type.
MXC_CPU_MX6D is not a real value in chip, so change it to 0x6A.Signed-off-by: Peng Fan
Cc: Stefano Babic
04 Oct, 2016
1 commit
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Add i.MX6ULL major cpu type.
Signed-off-by: Peng Fan
Signed-off-by: Ye Li
Cc: Stefano Babic
Reviewed-by: Stefano Babic
09 Mar, 2016
1 commit
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Read the number of cores in the fuses to distinguish between
the dual and solo versions.Tested on a mx7d sabresd and on a mx7solo warp7.
Signed-off-by: Fabio Estevam
Reviewed-by: Peng Fan
30 Oct, 2015
1 commit
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Move common chip revision id's to main cpu header file
mx25 generic include cpu header for chip revisionSigned-off-by: Adrian Alonso
13 Sep, 2015
2 commits
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Add imx7d basic SoC system support
Misc arch dependent functions for system bring upSigned-off-by: Adrian Alonso
Signed-off-by: Peng Fan
Signed-off-by: Ye.Li -
Add helper macro is_soc_type to identify iMX SoC family
Signed-off-by: Adrian Alonso
02 Sep, 2015
2 commits
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Since we need to support runtime check for different drivers, we need
to add get_cpu_rev for vf610, otherwise there will be build errors.This patch introduces a dummy CPU id which is not read from chip
silicon. Later when we can get the real id from chip, can fix the
value of MXC_CPU_VF610 then.Signed-off-by: Peng Fan
Suggested-by: Stefano Babic
Cc: Stefano Babic
Acked-by: Stefano Babic -
Add cpu types for i.MX2/3.
Signed-off-by: Peng Fan
Cc: Stefano Babic
Reviewed-by: Stefano Babic
02 Aug, 2015
2 commits
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Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from
DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which
is not real id from DIGPROG register, so change i.MX6D to value 0x67 which
was not occupied.Signed-off-by: Peng Fan
Signed-off-by: Ye.Li -
Add cpu type for i.MX6QP/DP.
This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP
and MXC_CPU_MX6DP, we should use:
(is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)).Signed-off-by: Peng Fan
Acked-by: Stefano Babic
17 Feb, 2015
1 commit
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Signed-off-by: Eric Nelson
20 Nov, 2014
1 commit
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Move MX5 specific set_chipselect_size function into generic i.MX part,
such that MX6 based boards are able to use this function as well.While doing this the iomuxc gpr member needed to be consolidated between
MX5 and MX6.Signed-off-by: Fabio Estevam
10 Jul, 2014
1 commit
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mx6solox is the newest member of the mx6 family.
Some of the new features on this variants are:
- Cortex M4 microcontroller (besides the CortexA9)
- Dual Gigabit EthernetAdd the initial support for it.
Signed-off-by: Fabio Estevam
11 Feb, 2014
2 commits
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Currently when we boot a mx6dual U-boot reports that it is a mx6quad.
Report it as MX6D instead:
CPU: Freescale i.MX6D rev1.2 at 792 MHz
Signed-off-by: Fabio Estevam
Acked-by: Stefano babic
Acked-by: Otavio Salvador -
Instead of duplicating the CPU definitions at mx5 and mx6 sys_proto.h header
files, introduce a common header to centralize such definitions.Signed-off-by: Fabio Estevam