27 Mar, 2014
1 commit
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I2C protocol requires open-drain IOs. Fix the Dalmore and Venice2 pinmux
tables to configure the IOs correctly. Without this, Tegra may actively
drive the lines high while an external device is actively driving the
lines low, which can only lead to bad things.Signed-off-by: Stephen Warren
Acked-by: Simon Glass
Signed-off-by: Tom Warren
25 Mar, 2014
1 commit
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Trivial merge conflict, needed to manually remove
local_info as per commit 41364f0f.Conflicts:
board/samsung/common/board.c
18 Mar, 2014
3 commits
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Add a simple LCD driver which uses SDL to display the image. We update the
image regularly, while still providing for reasonable performance.Adjust the common lcd code to support sandbox.
For command-line runs we do not want the LCD to be displayed, so add a
--show_lcd option to enable it.Tested-by: Che-Liang Chiou
Signed-off-by: Simon Glass -
Add board code to set up the Chrome OS EC on startup.
Signed-off-by: Simon Glass
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Add a common library for obtaining access to the Chrome OS EC. This is
used by boards which need to talk to the EC.Reviewed-by: Vadim Bendebury
Tested-by: Vadim Bendebury
Signed-off-by: Vadim Bendebury
Signed-off-by: Simon Glass
14 Mar, 2014
3 commits
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romImage is set by CONFIG_ECOVEC_ROMIMAGE_ADDR to 0xA0040000.
Signed-off-by: Baruch Siach
Signed-off-by: Nobuhiro Iwamatsu
13 Mar, 2014
5 commits
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Prior to Kbuild, $(TOPDIR) or $(SRCTREE) was used for
pointing to the top of source directory.
(No difference between the two.)In Kbuild style, $(srctree) is used for instead.
This commit renames SRCTREE to srctree and deletes the
defition of SRCTREE.Note that SRCTREE in scripts/kernel-doc, scripts/docproc.c,
doc/DocBook/Makefile should be keep.Signed-off-by: Masahiro Yamada
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Prior to Kbuild, $(TOPDIR) or $(SRCTREE) was used for
pointing to the top of source directory.
(No difference between the two.)In Kbuild style, $(srctree) is used instead.
This commit renames TOPDIR to srctree and delete the
defition of TOPDIR.Signed-off-by: Masahiro Yamada
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Signed-off-by: Masahiro Yamada
Cc: David Updegraff
Cc: Andre Schwarz -
- fix: return-value of 'i2c_set_bus_speed' was interpreted wrong
Signed-off-by: Hannes Petermaier
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The switch HW reset results in a disconnection of the switch port daisy-
chain for a few seconds. This is not desired in the normal field use
case. So lets remove this switch reset from the normal bootup sequence
and move it into a board specific command. This way it can be executed
in the development environment when really needed.Signed-off-by: Stefan Roese
Cc: Roger Meier
Cc: Lukas Stockmann
Cc: Tom Rini
12 Mar, 2014
9 commits
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This patch enables to run Trats2 board on device tree.
Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
Signed-off-by: Minkyu Kang -
This patch enables to run Trats board on device tree.
Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
CC: Lukasz Majewski
Signed-off-by: Minkyu Kang -
This patch enables to run Universal board on device tree.
Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
Acked-by: Przemyslaw Marczak
Signed-off-by: Minkyu Kang -
This patch enables to run Origen board on device tree.
Uart, DRAM and MMC init functions are removed as their
generic replacements form the common board file are used.The config file is modified to contain only board specific options.
Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
Cc: Chander Kashyap
Signed-off-by: Minkyu Kang -
This patch enables sdhci initialisation and misc_init_r in common board
file for all exynos 4 based boards.Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
Signed-off-by: Minkyu Kang -
This patch moves board specific max77686 init function from
common board to smdk5250 board file.Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
Cc: Rajeshwari S Shinde
Cc: Rajeshwari Birje
Signed-off-by: Minkyu Kang -
This patch adds common dtsi file and config header for all
Exynos 4 based boards.Patch additionaly adds board specific (weak) functions for
board_early_init_f and board_power_init functions.Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
Signed-off-by: Minkyu Kang -
The checkboard function's implementation is common for all
DT supporting boards and should be placed in the board common file.Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
Cc: Chander Kashyap
Cc: Rajeshwari S Shinde
Cc: AmarAcked-by: Rajeshwari Shinde
Signed-off-by: Minkyu Kang -
Gateworks Ventana is a product family based on the i.MX6. This
patch adds support for all boards in the Ventana family. Where
possible, data from the boards EEPROM is used to determine various
details about the board at runtime.Signed-off-by: Tim Harvey
11 Mar, 2014
4 commits
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Many USB host controller drivers contain almost identical copies of the
same virtual root hub descriptors. Put these into a common file to avoid
duplication.Note that there were some very minor differences between the descriptors
in the various files, such as:- USB 1.0 vs. USB 1.1
- Manufacturer/Device ID
- Max packet size
- String contentI assume these aren't relevant.
Cc: Thomas Lange
Cc: Shinya Kuribayashi
Cc: Gary Jennejohn
Cc: Wolfgang Denk
Cc: Eric Millbrandt
Cc: Pierre Aubert
Cc: Stefan Roese
Cc: Daniel Hellstrom
Cc: Denis Peter
Cc: Rodolfo Giometti
Cc: Zhang Wei
Cc: Mateusz Zalega
Cc: Remy Bohmer
Cc: Markus Klotzbuecher
Cc: Minkyu Kang
Cc: Gary Jennejohn
Cc: C Nauman
Cc: David Müller
Cc: Yoshihiro Shimoda
Cc: Nobuhiro Iwamatsu
Cc: Thomas Abraham
Cc: Tom Rini
Cc: Andrew Murray
Cc: Matej Frančeškin
Cc: Cliff Cai
Cc: Bryan Wu
Signed-off-by: Stephen Warren -
Signed-off-by: Ian Campbell
Acked-by: Rob Herring
10 Mar, 2014
5 commits
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CONFIG_SYS_HZ must be always 1000, but M5271EVB.h defines it
as 1000000 and idmr.h defines it as (50000000 / 64).When compiling these two boards, a warning message is displayed:
time.c:14:2: warning: #warning "CONFIG_SYS_HZ must be 1000
and should not be defined by platforms" [-Wcpp]There are no board maintainers for them so this commit just
deletes them.Signed-off-by: Masahiro Yamada
Cc: Jason Jin -
Add NAND SPL boot support with hardware PMECC.
Signed-off-by: Bo Shen
Signed-off-by: Andreas Bießmann -
Add SPI SPL boot support for sama5d3xek board.
Signed-off-by: Bo Shen
Signed-off-by: Andreas Bießmann -
Add sama5d3 Xplained board support which use Atmel SAMA5D36 SoC.
Now it supports boot from NAND flash and SD/MMC card.
Features support:
- NAND flash
- SD/MMC card
- Two USB hosts
- Ethernet (one GMAC, one EMAC)Signed-off-by: Bo Shen
[reorder boards.cfg]
Signed-off-by: Andreas Bießmann -
Add support for using the Atmel MCI driver on at91sam9263ek.
This change is modeled after the existing at91sam9260ek support.Please note that this hooks up slot1 (MCI1) for SD. Not both.
Tested with at91bootstrap and u-boot on dataflash in slot 0
and fat-formatted 8GB SDHC in slot 1 on first revision
at91sam9263ek (which must use dataflash in slot0 to boot).CONFIG_ATMEL_MCI_PORTB not tested.
Signed-off-by: Andreas Henriksson
[remove empty line]
Signed-off-by: Andreas Bießmann
08 Mar, 2014
9 commits
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Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
two Chip selects.
-Update board_specific_parameters udimm structure with settings
derived via calibration.
-Update ddr_raw_timing sructure corresponding to DIMM.
-Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
but on T104xRDB, on setting this , DDR instability is observed.
Board-level debugging is in progress.Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.Signed-off-by: Priyanka Jain
Signed-off-by: York Sun -
T1040 has internal display interface unit (DIU) for driving video.
T1040QDS supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoderChrontel, CH7301C encoder which is I2C programmable is used as
HDMI connector on T1040QDS.
This patch add support to
-enable Video interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on boardSigned-off-by: Priyanka Jain
Reviewed-by: York Sun -
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
It works in two mode: standalone mode and PCIe endpoint mode.T2080PCIe-RDB Feature Overview
------------------------------
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
DDR Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LP devices
- 72bit 4GB DDR3-LP SODIMM in slot
Ethernet interfaces:
- Two 10M/100M/1G RGMII ports on-board
- Two 10Gbps SFP+ ports on-board
- Two 10Gbps Base-T ports on-board
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes 16 lanes configuration:
- SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
- SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
- SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
- SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
- SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
- SerDes-2 Lane G-H: to SATA1 & SATA2
IFC/Local Bus:
- NOR: 128MB 16-bit NOR flash
- NAND: 512MB 8-bit NAND flash
- CPLD: for system controlling with programable header on-board
eSPI:
- 64MB N25Q512 SPI flash
USB:
- Two USB2.0 ports with internal PHY (both Type-A)
PCIe:
- One PCIe x4 gold-finger
- One PCIe x4 connector
- One PCIe x2 end-point device (C293 Crypto co-processor)
SATA:
- Two SATA 2.0 ports on-board
SDHC:
- support a TF-card on-board
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial portsSigned-off-by: Shengzhou Liu
Reviewed-by: York Sun -
Change QIXIS timing parameter CONFIG_SYS_CS3_FTIM2 to 8 from 0.
Fix EMI2 for t2080qds, which was caused by adding t2081qds.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384)
and at cold temperatures(A006475), workaround recalibrate the
PLLs with some SerDes configurationBoth these errata are only applicable for b4 rev1.
So, make workaround for these errata conditional,
depending upon soc version.Signed-off-by: Shaveta Leekha
Reviewed-by: York Sun -
Change setting of SerDes2 refclk2 to have the default value as it is
coming on board that is 156.25MHz, for XFI to work.
Also change PLL_NUM variable to the one defined in config_mpc85xx.h
for B4860 and B4420.Signed-off-by: Shaveta Leekha
Reviewed-by: York Sun -
On B4860 and B4420, some serdes protocols can be used with LC VCO as
well as Ring VCO options.Addded Alternate options with LC VCO for such protocols.
For example protocol 0x2a on srds 1 becomes 0x29 if it is LC VCO.The alternate option has the same functionality as the original option;
the only difference being LC VCO rather than Ring VCO.Signed-off-by: Poonam Aggrwal
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
1) SerDes2 Refclks have been set properly to make
PCIe SATA to work as it work on SerDes refclk of 100MHz
2) Mask the SerDes's device reset request before changing
the Refclks for SerDes1 and SerDes2 for PLL locks to
happen properly, device reset request bit unmasked
after SerDes refclks configurationSigned-off-by: Shaveta Leekha
Reviewed-by: York Sun
