30 Aug, 2016
1 commit
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On i.MX6ULL, according to the latest REFTOP_TRIM fuse define, we need
to set the REFTOP_VBGADJ bits in PMU_MISC0 register as below table:'000" - set REFTOP_VBGADJ[2:0] to 3'b000
'001" - set REFTOP_VBGADJ[2:0] to 3'b001
'010" - set REFTOP_VBGADJ[2:0] to 3'b010
'011" - set REFTOP_VBGADJ[2:0] to 3'b011
'100" - set REFTOP_VBGADJ[2:0] to 3'b100
'101" - set REFTOP_VBGADJ[2:0] to 3'b101
'110" - set REFTOP_VBGADJ[2:0] to 3'b110
'111" - set REFTOP_VBGADJ[2:0] to 3'b111Signed-off-by: Bai Ping
(cherry picked from commit b2690f5cf54390999acb2f1f7b788bfd18fa11be)
25 Aug, 2016
1 commit
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Per to design team, we need to set REFTOP_VBGADJ
in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the
actually table is as below:'000' - set REFTOP_VBGADJ[2:0] to 3b'110
'110' - set REFTOP_VBGADJ[2:0] to 3b'000
'001' - set REFTOP_VBGADJ[2:0] to 3b'001
'010' - set REFTOP_VBGADJ[2:0] to 3b'010
'011' - set REFTOP_VBGADJ[2:0] to 3b'011
'100' - set REFTOP_VBGADJ[2:0] to 3b'100
'101' - set REFTOP_VBGADJ[2:0] to 3b'101
'111' - set REFTOP_VBGADJ[2:0] to 3b'111Signed-off-by: Bai Ping
29 Jul, 2016
1 commit
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add splash screen feature for epdc.
it's tested on imx6ull arm2 board.Signed-off-by: Robby Cai
22 Jul, 2016
1 commit
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For i.MX6, the mux width is 4, not 3. So enlarge the width.
Signed-off-by: Peng Fan
19 Jul, 2016
1 commit
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Add configs and board level codes for i.MX6ULL 14x14 EVK. Very similar
board from i.MX6UL EVK. I2C, UART, USB, QSPI, SD, ENET and LCD are ok
to work.The codes for i.MX6ULL 9x9 EVK is kept. We will add 9x9 build target when
it is needed.The DDR3 script is using version 1.2:
File: EVK_IMX6ULL_DDR3L_400MHz_512MB_16bit_V1.2_NewDRAM.inc
Test: 3 boards passed memtester.
Build target:
mx6ull_14x14_evk_defconfig
Signed-off-by: Ye Li
15 Jul, 2016
1 commit
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Need to gate ENET clock when switching to a new clock parent, because
the mux is not glitchless.Signed-off-by: Ye.Li
08 Jun, 2016
1 commit
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Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage
is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0
bit[6:4]) setting to 2b'110.Signed-off-by: Bai Ping
16 May, 2016
1 commit
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SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
not in IOMUXC, so correct the related registers' offset.Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
them from iomuxc pins.Define CONFIG_IOMUX_LPSR for mx6ull_ddr3_arm2 board to enable
using these pins.Signed-off-by: Peng Fan
10 May, 2016
1 commit
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Several UART input selects are missing. The fourth input select
for UART2_TX_DATA_ALT0 is actually also missing in the documentation.
(at least in Rev. B of the i.MX 7Dual Reference Manual). However,
when looking at the tables of other input selects, it is very natural
that there must be an input select for the UART2_TX_DATA_ALT0 pad.
The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and
it was required to set that particular input select register to get a
working UART2.From https://www.mail-archive.com/u-boot@lists.denx.de/msg211942.html
Signed-off-by: Peng Fan
09 May, 2016
1 commit
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Fix runtime checking for i.MX6ULL. Add is_cpu_type(MXC_CPU_MX6ULL)
to avoid using wrong code path.Signed-off-by: Peng Fan
07 May, 2016
1 commit
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This patch is a porting of
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38
"
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to gf/2 and if bitflip detected, GPMI driver will
correct the data to all 0xFF.Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
with the one for i.MX6QP.
"In this patch, i.MX6UL is added and threshold changed to use ecc_strength.
Signed-off-by: Peng Fan
06 May, 2016
1 commit
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The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).Signed-off-by: Stefan Agner
04 May, 2016
1 commit
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According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.
"So If L2 cache is already enabled, chaning value of ACR will cause SLVERR,
uboot hangs.In some cases, such as plugin, L2 Cache enabled bit is not cleared,
then "Set bit 22 in the auxiliary control register" cause uboot hangs.Signed-off-by: Peng Fan
03 May, 2016
1 commit
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2016 u-boot added dummy CPU types for the i.MX6QP and i.MX6DP. When
doing runtime cpu type checking, we can't use CPU type of i.MX6Q and
i.MX6D for them more, which is ok in 2015 u-boot.This patch adds the MXC_CPU_MX6QP and MXC_CPU_MX6DP at some places missed to
do the checking.Signed-off-by: Ye Li
28 Apr, 2016
1 commit
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Correct speed grading info for i.MX6UL
Signed-off-by: Peng Fan
21 Apr, 2016
1 commit
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To align with other i.mx6 platforms, update config file to remove some
unnecessary settings. Also enable the GPIO command.Signed-off-by: Ye Li
15 Apr, 2016
1 commit
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Adjust POR_B settings on i.MX6ULL according to design
team's suggestion:2'b00 : always PUP100K
2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL
2'b10 : always disable PUP100K
2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended settingSigned-off-by: Anson Huang
13 Apr, 2016
10 commits
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Support mx6ull ddr3 arm2 board.
DDR script version 1.1. Passed memtester on 3 boards.Take mx6ul 14x14 ddr3 arm2 as reference.
Note:
LCD/NAND/ECSPI not tested, need hardware rework.Signed-off-by: Peng Fan
(cherry picked from commit 584050b98cf070bb608b652e89659ff20c47efba) -
Since the mx6ull adds the AIPS3, so enable its initialization.
Signed-off-by: Ye Li
(cherry picked from commit f774a4c12b8ef197483075bbcd840b3ea27308e9) -
Update memory map address for mx6ull which uses AIPS3 and adjust UART8
to AIPS3 by replacing for ESAI.Signed-off-by: Ye Li
(cherry picked from commit 5154e0c15965019602a7c128abe00d58b6e26ff1) -
Update CCM registers and clock settings according the mx6ull changes
Signed-off-by: Ye Li
(cherry picked from commit 60cb811a0e9abbdd89e498c499fa4e63a18fae58) -
Rom already initialized clock at 396M and 132M for arm core and ahb
Signed-off-by: Peng Fan
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The PFD reset is not needed for mx6ull, since it uses runtime cpu id
checking here, add codes to skip it.Signed-off-by: Ye Li
(cherry picked from commit 4543971c6078410078efbc830b9fc86363e7bebd) -
The MX6ULL has GPT with supporting OSC clock source, update the driver
accordingly.Signed-off-by: Ye Li
(cherry picked from commit b2740fd7a0f8d80b416d4de1f57b6542407d23bd) -
Since iMX6ULL is derivative of iMX6UL, most of design are same, so enable
CONFIG_MX6UL to reduce duplicated effort.We can use CONFIG_MX6ULL for the difference between these two chips.
Signed-off-by: Ye Li
(cherry picked from commit b3b0a429ef66d334e776052c1a9a281aeb568e05) -
Add MXC_CPU_MX6ULL for i.MX6ULL CPU ID
Signed-off-by: Ye Li
(cherry picked from commit 7377004dfc8d5d01f6ca7899f6355a0ac4ea7f8a) -
Add iomux headers according the file SDK_IOMaps_i.MX6ULL_Headers_b151218.zip
Signed-off-by: Ye Li
(cherry picked from commit a78b5b07bd8f15f6c896d85289174e7ed0fc76c1)
28 Mar, 2016
1 commit
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We have runtime checking now, since SNVS_LP_BASE_ADDR is only for i.MX6UL
now, so it will break building for other i.MX6[x].Introduce MX6UL_SNVS_LP_BASE_ADDR to avoid build break.
Signed-off-by: Peng Fan
25 Mar, 2016
12 commits
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From TO1.1, SNVS adds internal pull up control for POR_B,
the register filed is GPBIT[1:0], after system boot up,
it can be set to 2b'01 to disable internal pull up.
It can save about 30uA power in SNVS mode.Signed-off-by: Anson Huang
(cherry picked from commit 5fd1cb94781926dca4bfdc2804f2550dcd6b65a5) -
Change to use #ifdef not the IS_ENABLED, because we will get build warning
when the CONFIG_IMX_RDC is not set.Signed-off-by: Ye Li
-
No need to set ahb clock for i.MX6UL, since rom code already
configured the clock at the freq 396M/132MSigned-off-by: Peng Fan
-
On mx7d 12x12 lpddr3 arm2 board, POR_B reset in uboot will fail stress
reset test, and hangs in rom code. Rom log buffer show thats wrong
hab_image_entry and runs into serial download mode. Also there is no
time delay reset circuit for this board.We found when disable CONFIG_VIDEO, all seems fine. Actually,
only the following piece of code can make stress reset ok,
"
writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
while (--timeout) {
if (readl(®s->hw_lcdif_ctrl1) & LCDIF_CTRL1_VSYNC_EDGE_IRQ)
break;
udelay(1);
}
"
Here we use lcdif_power_down API which is better to shutdown lcdif same as
the way used in arch_preboot_os.Implement reset_misc for mx7, since it does not hurt for others boards.
Signed-off-by: Peng Fan
(cherry picked from commit cd1bd6ee94e720af911a2ce7db697af0df59c0a9) -
Update settings for PRE. Value for Saturation THR of PREx,
changed from 0x20 to 0x10 to make system more stable.Signed-off-by: Peng Fan
(cherry picked from commit 02e7090604e55d9690532294b02b499609d46e63)
(cherry picked from commit f7c5cf580fcc2c8ab95a8d835f5874d26216910f) -
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17]
for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit,
the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake
never clears.Signed-off-by: Ye Li
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Add the fuse checking in drivers, when the module is disabled in fuse,
the driver will not work.Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
USB-EHCI, GIS, LCDIF.Signed-off-by: Ye Li
-
Implement a functionality to read the soc fuses and check if any module
is fused. For fused module, we have to disable it in u-boot dynamically,
and change the its node in FDT to "disabled" status before starting the kernel.In this patch, we implement the ft_system_setup for FDT fixup. This function will
be called during boot process or by "fdt systemsetup" command.To enable the module fuse checking, two configurations must be defined:
CONFIG_MODULE_FUSE
CONFIG_OF_SYSTEM_SETUPSigned-off-by: Ye Li
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Need to check cpu type for i.MX6SOLO for the HAB functions addresses.
Signed-off-by: Ye Li
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Debug monitor will print out last failed AXI access info when
system reboot is caused by AXI access failure, only works when
debug monitor is enabled.Enable this module on i.MX6SX.
Signed-off-by: Anson Huang
Signed-off-by: Ye.Li
(cherry picked from commit df6ac8531d498021ed379c74fc1847bd2cec7179)
Signed-off-by: Peng Fan -
Since the following piece settings can not be in DCD table, we
add them in enable_ipu_clock.
"
setmem /32 0x00bb048c = 0x00000002 ## Bypass IPU1 QoS generator
setmem /32 0x00bb050c = 0x00000002 ## Bypass IPU2 QoS generator
setmem /32 0x00bb0690 = 0x00000200 ## Bandwidth THR for of PRE0
setmem /32 0x00bb0710 = 0x00000200 ## Bandwidth THR for of PRE1
setmem /32 0x00bb0790 = 0x00000200 ## Bandwidth THR for of PRE2
setmem /32 0x00bb0810 = 0x00000200 ## Bandwidth THR for of PRE3
setmem /32 0x00bb0694 = 0x00000020 ## Saturation THR for of PRE0
setmem /32 0x00bb0714 = 0x00000020 ## Saturation THR for of PRE1
setmem /32 0x00bb0794 = 0x00000020 ## Saturation THR for of PRE2
setmem /32 0x00bb0814 = 0x00000020 ## Saturation THR for of PRE
"
CONFIG_VIDEO_IPUV3 is always defined in mx6sabre_common.h,
the settings sure will effect.Signed-off-by: Peng Fan
(cherry picked from commit 61cec88a59ebf450dd1352d81e03b5aa842e1d71) -
Apply errata based on PL310 version instead of compile
time. Also set Prefetch offset to 15, since it improves
memcpy performance by 35%. Don't enable Incr double
Linefill enable since it adversely affects memcpy
performance by about 32MB/s and reads by 90MB/s. Tested
with 4K to 16MB sized src and dst aligned buffer.Signed-off-by: Nitin Garg
(cherry picked from commit 31751fa9cf29ef4056f49fe06a54700a89c9bdc5)
