26 Apr, 2014
2 commits
24 Apr, 2014
2 commits
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add support for the ids8313 board.
CPU: e300c3, MPC8313, Rev: 2.1 at 396 MHz, CSB: 132 MHz
I2C: ready
SPI: ready
DRAM: 128 MiB (DDR2, 32-bit, ECC off, 264 MHz)
Flash: 8 MiB
NAND: 128 MiB
Net: TSEC0, TSEC1 [PRIME]public key on NOR flash start
Signed-off-by: Heiko Schocher
Signed-off-by: Kim Phillips -
create vendor board directory ids and move ids8247 board to it.
Signed-off-by: Heiko Schocher
Cc: Wolfgang Denk
Signed-off-by: Kim Phillips
23 Apr, 2014
14 commits
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Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND boot, fix it.Signed-off-by: Shaohui Xie
Reviewed-by: York Sun -
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control
to u-boot.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers
control to u-boot.Signed-off-by: Shengzhou Liu
[York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH]
Reviewed-by: York Sun -
Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordinglySigned-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Add support of 2 stage NAND boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordinglySigned-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
T1040RDB, T1042RDB header files are very similar so merged into new header file T104xRDB.
T104xRDB header file can support both T1040RDB and T1042RDB_PI header.Patch makes following changes
-Update Boards.cfg file for T1040RDB and T1042RDB_PI
-Add new T104xRDB header file
-Delete T1040RDB, T1042RDB_PI header fileSigned-off-by: Vijay Rai
Signed-off-by: Priyanka Jain
Reviewed-by: York Sun -
T1040QDS_D4 is a variant of T1040QDS, with additional circuit to support
DDR4 memory. Tested with MTA9ASF51272AZ-2G1AYESZG.Signed-off-by: York Sun
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Secure Boot Target is added for T1040QDS and T1040RDB
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and
CONFIG_T1040RDBSigned-off-by: Gaurav Rana
Signed-off-by: Aneesh Bansal
Reviewed-by: York Sun -
Secure Boot Target is added for T2080QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS.Signed-off-by: Aneesh Bansal
Reviewed-by: York Sun -
Secure Boot Target is added for T4240QDS and T4160QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS.Signed-off-by: Aneesh Bansal
Reviewed-by: York Sun -
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
keeping area. This configuration is to be disabled once in uboot.
Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
As a result cache invalidation function was getting skipped in
case CPC is configured as SRAM.This was causing random crashes.Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
Reviewed-by: York Sun -
In case of secure boot from NAND, the DDR is initialized by the
BootROM using the config words (CF_WORDS) in the CF_HEADER
and u-boot image is copied from NAND to DDR by the BootROM.
So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NANDSigned-off-by: Aneesh Bansal
Reviewed-by: York Sun -
Add NOR, SPI and SD secure boot targets for BSC9132QDS.
Changes:
- Debug TLB entry is not required for Secure Boot Target.Signed-off-by: Aneesh Bansal
Reviewed-by: York Sun -
For KVM we have a special PV machine type called "ppce500". This machine
is inspired by the MPC8544DS board, but implements a lot less features
than that one.It also provides more PCI slots and is supposed to be enumerated by
device tree only.This patch adds support for the generic ppce500 machine and tries to
rely solely on device tree for device enumeration.Signed-off-by: Alexander Graf
Acked-by: Scott Wood
Reviewed-by: York Sun
20 Apr, 2014
1 commit
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This is dead hardware and no one is interested in making the
necessary changes for upcoming features like generic board or
driver model.Signed-off-by: Daniel Schwierzeck
Cc: Wolfgang Denk
18 Apr, 2014
11 commits
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Enough time has passed since this board was moved to Orphan. Remove.
- Remove board/lubbock/*
- Remove include/configs/lubbock.h
- Cleanup defined(CONFIG_LUBBOCK)
- Move the entry from boards.cfg to doc/README.scrapyardSigned-off-by: Masahiro Yamada
-
Enough time has passed since this board was moved to Orphan. Remove.
- Remove include/configs/EVB64260.h
- Remove the entry from boards.cfgSigned-off-by: Masahiro Yamada
-
Enough time has passed since this board was moved to Orphan. Remove.
- Remove board/mousse/*
- Remove include/configs/MOUSSE.h
- Clean-up defined(CONFIG_MOUSSE)
- Move the entry from boards.cfg to doc/README.scrapyardSigned-off-by: Masahiro Yamada
-
Enough time has passed since this board was moved to Orphan. Remove.
- Remove board/rsdproto/*
- Remove include/configs/rsdproto.h
- Move the entry from boards.cfg to doc/README.scrapyardSigned-off-by: Masahiro Yamada
-
Enough time has passed since this board was moved to Orphan. Remove.
- Remove board/rpxsuper/*
- Remove include/configs/RPXsuper.h
- Move the entry from boards.cfg to doc/README.scrapyardSigned-off-by: Masahiro Yamada
-
Enough time has passed since these boards were moved to Orphan. Remove.
- Remove board/RPXlite/*
- Remove board/RPXClassic/*
- Remove include/configs/RPXlite.h
- Remove include/configs/RPXClassic.h
- Clean-up defined(CONFIG_RPXCLASSIC)
- Move the entry from boards.cfg to doc/README.scrapyardSigned-off-by: Masahiro Yamada
-
Enough time has passed since these boards were moved to Orphan. Remove.
- Remove include/configs/{ADS860.h,FADS823.h,FADS850SAR.h,FADS860T.h}
- Cleanup defined(CONFIG_ADS), defined(CONFIG_MPC823FADS),
defined(CONFIG_MPC850SAR), defined(CONFIG_SYS_DAUGHTERBOARD)
- Remove the entries from boards.cfgSigned-off-by: Masahiro Yamada
-
Enough time has passed since this board was moved to Orphan. Remove.
- Remove board/genietv/*
- Remove include/configs/GENIETV.h
- Clean-up if defined(CONFIG_GENIETV)
- Move the entry from boards.cfg to doc/README.scrapyardSigned-off-by: Masahiro Yamada
-
Enough time has passed since these boards were moved to Orphan. Remove.
- Remove board/mbx8xx/*
- Remove include/configs/{MBX.h,MBX860T.h}
- Clean-up if defined(CONFIG_MBX)
- Move the entries from boards.cfg to doc/README.scrapyardSigned-off-by: Masahiro Yamada
-
Enough time has passed since this board was moved to Orphan. Remove.
- Remove board/nx823/*
- Remove include/configs/NX823.h
- Clean-up ifdef(CONFIG_NX823)
- Move the entry from boards.cfg to doc/README.scrapyardSigned-off-by: Masahiro Yamada
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Emails to the following addresses have been bouncing.
- Nye Liu
- Jim Thompson
- Brad KempSigned-off-by: Masahiro Yamada
25 Mar, 2014
1 commit
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Trivial merge conflict, needed to manually remove
local_info as per commit 41364f0f.Conflicts:
board/samsung/common/board.c
14 Mar, 2014
1 commit
12 Mar, 2014
1 commit
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Gateworks Ventana is a product family based on the i.MX6. This
patch adds support for all boards in the Ventana family. Where
possible, data from the boards EEPROM is used to determine various
details about the board at runtime.Signed-off-by: Tim Harvey
11 Mar, 2014
3 commits
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Some recent changes got parts of the file out of order again, correct.
Signed-off-by: Tom Rini
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When I cc board maintainers, some of them result in
bounce mails.It turned out the following do not work any more:
Yuli Barcohen
Travis Sawyer
Yusdi Santoso
David Updegraff
Sangmoon Kim
Anton Vorontsov
Blackfin Team
Bluetechnix Tinyboards
Andre SchwarzFor the blackfin boards where Sonic Zhang is also listed
as a maintainer, dead addresses should be simply dropped.For all of the others, the status should be changed to "Orphan".
We have adopted the definition of "Orphan" as:
board is not actively maintained any more but still builds, and any
address associated with it is that of the last known maintainer(s)Even though the emails do not work any more, they carry information.
We want to keep them.Besides, Orphan boards have been collected at the bottom of boards.cfg.
(This is done when we run "tools/reformat.py")Add separators to distinguish them from those which
were moved to Orphan 6 months ago.
I believe it will be helpful in future to find which boards are
old enough to be removed from the code base.Signed-off-by: Masahiro Yamada
Cc: Detlev Zundel
Cc: Tom Rini
Cc: Albert ARIBAUD
10 Mar, 2014
2 commits
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CONFIG_SYS_HZ must be always 1000, but M5271EVB.h defines it
as 1000000 and idmr.h defines it as (50000000 / 64).When compiling these two boards, a warning message is displayed:
time.c:14:2: warning: #warning "CONFIG_SYS_HZ must be 1000
and should not be defined by platforms" [-Wcpp]There are no board maintainers for them so this commit just
deletes them.Signed-off-by: Masahiro Yamada
Cc: Jason Jin -
Add sama5d3 Xplained board support which use Atmel SAMA5D36 SoC.
Now it supports boot from NAND flash and SD/MMC card.
Features support:
- NAND flash
- SD/MMC card
- Two USB hosts
- Ethernet (one GMAC, one EMAC)Signed-off-by: Bo Shen
[reorder boards.cfg]
Signed-off-by: Andreas Bießmann
08 Mar, 2014
2 commits
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T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
It works in two mode: standalone mode and PCIe endpoint mode.T2080PCIe-RDB Feature Overview
------------------------------
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
DDR Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LP devices
- 72bit 4GB DDR3-LP SODIMM in slot
Ethernet interfaces:
- Two 10M/100M/1G RGMII ports on-board
- Two 10Gbps SFP+ ports on-board
- Two 10Gbps Base-T ports on-board
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes 16 lanes configuration:
- SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
- SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
- SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
- SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
- SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
- SerDes-2 Lane G-H: to SATA1 & SATA2
IFC/Local Bus:
- NOR: 128MB 16-bit NOR flash
- NAND: 512MB 8-bit NAND flash
- CPLD: for system controlling with programable header on-board
eSPI:
- 64MB N25Q512 SPI flash
USB:
- Two USB2.0 ports with internal PHY (both Type-A)
PCIe:
- One PCIe x4 gold-finger
- One PCIe x4 connector
- One PCIe x2 end-point device (C293 Crypto co-processor)
SATA:
- Two SATA 2.0 ports on-board
SDHC:
- support a TF-card on-board
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial portsSigned-off-by: Shengzhou Liu
Reviewed-by: York Sun