08 Sep, 2011
12 commits
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Signed-off-by: Wolfgang Denk
Cc: Albert ARIBAUD
Cc: Marek Vasut
Acked-by: Marek Vasut -
Signed-off-by: Wolfgang Denk
Cc: Albert ARIBAUD
Cc: Rolf Offermanns -
Signed-off-by: Wolfgang Denk
Cc: Albert ARIBAUD
Cc: Thomas Elste -
Signed-off-by: Wolfgang Denk
Cc: Albert ARIBAUD -
Signed-off-by: Wolfgang Denk
Cc: Albert ARIBAUD
Cc: Alex Züpke -
Signed-off-by: Wolfgang Denk
Cc: Albert ARIBAUD
Cc: Marius Gröger -
Signed-off-by: Wolfgang Denk
Cc: Albert ARIBAUD
Cc: George G. Davis -
Signed-off-by: Wolfgang Denk
Cc: Albert ARIBAUD
Cc: Curt Brune -
Signed-off-by: Wolfgang Denk
Cc: Albert ARIBAUD
Cc: Marius Gröger -
Signed-off-by: Wolfgang Denk
Cc: Albert ARIBAUD
Cc: Alex Züpke -
Signed-off-by: Wolfgang Denk
Cc: Albert ARIBAUD -
Signed-off-by: Wolfgang Denk
04 Sep, 2011
18 commits
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c2dd0d45540397704de9b13287417d21049d34c6 added dcache_enable()
to board_init_r(). This enables d-cache for all ARM boards.
As a result some of the arm boards that are not cache-ready
are broken. Revert this change and allow platform code to
take the decision on d-cache enabling.Also add some documentation for cache usage in ARM.
Signed-off-by: Aneesh V
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Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
Cc: Stelian Pop -
Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
Cc: Gary Jennejohn -
Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
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Remove lpd7a400 and lpd7a404 boards.
Signed-off-by: Wolfgang Denk
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Remove edb9301, edb9302, edb9302a, edb9307, edb9307a, edb9312,
edb9315 and edb9315a boards.Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
Cc: Andrea Scian -
Signed-off-by: Wolfgang Denk
Cc: Rowel Atienza -
Signed-off-by: Wolfgang Denk
Cc: George G. Davis -
This is a port of the official PLL errata workaround from Freescale to
mainline u-boot.
The PLL's in the i.MX51 processor can go out of lock due to a metastable
condition in an analog flip-flop when used at high frequencies.
This workaround implements an undocumented feature in the PLL (dither
mode), which causes the effect of this failure to be much lower (in terms
of frequency deviation), avoiding system failure, or at least decreasing
the likelihood of system failure.Signed-off-by: David Jander
09 Aug, 2011
1 commit
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This describes what it is for, devices supported, how to enable for your
board in U-Boot, setting up the server, and notes about MAC addresses.Signed-off-by: Simon Glass
Tested-by: Eric Bénard
05 Aug, 2011
1 commit
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There was a mix of UTF-8 and ISO-8859 files in the U-Boot source
tree, which could cause issues with the patchwork review system.
This commit converts all ISO-8859 files to UTF-8.Signed-off-by: Albert ARIBAUD
03 Aug, 2011
1 commit
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Since all currently supported at91rm9200 boards are migrated to at91
support the joining notice can be removed.Signed-off-by: Andreas Bießmann
29 Jul, 2011
1 commit
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Recieve/Receive
recieve/receive
Interupt/Interrupt
interupt/interrupt
Addres/Address
addres/addressSigned-off-by: Mike Williams
28 Jul, 2011
1 commit
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creating an u-boot.ubl file, which contains the UBL Header
needed for booting from NAND with the RBL from TI. For more
information read doc/README.ublimage.Signed-off-by: Heiko Schocher
26 Jul, 2011
2 commits
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Command calls update_tftp() analogous to automatic update described
in doc/README.update.Usage:
fitupd [addr]
- run update from FIT image at addr
or from tftp 'updatefile'Signed-off-by: Andreas Pretzsch
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Signed-off-by: Aneesh V
Signed-off-by: Daniel Schwierzeck
18 Jul, 2011
1 commit
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P2041RDB Specification:
-----------------------
Memory subsystem:
* 4Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
* 128 Mbyte NOR flash single-chip memory
* 256 Kbit M24256 I2C EEPROM
* 16 Mbyte SPI memory
* SD connector to interface with the SD memory cardEthernet:
* dTSEC1: connected to the Vitesse SGMII PHY (VSC8221)
* dTSEC2: connected to the Vitesse SGMII PHY (VSC8221)
* dTSEC3: connected to the Vitesse SGMII PHY (VSC8221)
* dTSEC4: connected to the Vitesse RGMII PHY (VSC8641)
* dTSEC5: connected to the Vitesse RGMII PHY (VSC8641)PCIe:
* Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1
* Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors
USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces
I2C:
* I2C1: Real time clock, Temperature sensor, Memory module
* I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Mingkai Hu
Signed-off-by: Kumar Gala
12 Jul, 2011
2 commits
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Specify hwconfig usage for USB mode and phy change
Signed-off-by: Ramneek Mehresh
Signed-off-by: Kumar Gala -
The P1023RDS board is the reference board for the P1023 SoC.
Add support for booting it from NOR or NAND, with fixed 2G of DDR, PCIe,
UART, I2C, etc.Signed-off-by: Roy Zang
Signed-off-by: Haiying Wang
Signed-off-by: Chunhe Lan
Signed-off-by: Lei Xu
Signed-off-by: York Sun
Signed-off-by: Kumar Gala
