06 Oct, 2014
40 commits
-
Move icache_enable() and dcache_enable() function calls from
board code into the CPU code and into the enable_caches()
function. This is how the cache enabling code was designed
to work.Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc: Marek Vasut
Cc: Tom Rini
Cc: Albert Aribaud
Cc: Wolfgang Denk
Acked-by: Pavel Machek -
Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit.
Enable the bootz command as zImage is used instead uImage.Signed-off-by: Chin Liang See
Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc: Marek Vasut
Cc: Tom Rini
Cc: Albert Aribaud
Cc: Wolfgang Denk
Acked-by: Pavel Machek -
Enable the DesignWare MMC controller driver support
for SOCFPGA Cyclone5 dev kitSigned-off-by: Chin Liang See
Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc: Marek Vasut
Cc: Tom Rini
Cc: Albert Aribaud
Cc: Wolfgang Denk
Acked-by: Pavel Machek -
Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA .
The code sets the access permissions for the CPU to the AMBA slaves such
that the CPU can access them in both secure and non-secure mode.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek -
Configure the PL310 address filter to make sure DRAM is mapped to 0x0.
This code also configures the "remap" register of NIC-301 and sets the
required 'mpuzero' bit.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Add register definition for the NIC-301 used on SoCFPGA.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Add the Snoop Control Unit register definition file.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Enable the PL310 L2 cache controller support for the SoCFPGA.
With the cache related issues resolved, this is safe to be done.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
The Cortex-A9 has 32-byte long L1 cachelines. Define this value.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Add missing system manager bits from Altera U-Boot to make the code
comparable. These are the bits which depend on the FPGA manager.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Add function to enable and disable FPGA bridges. This code is used
by the FPGA manager to disable the bridges before programming the
FPGA and will later be also used by the initialization code for the
chip to put the chip into well defined state during startup.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel MachekV2: Move the not-CPU specific stuff into drivers/fpga/ and base
this on the cleaned up altera FPGA support. -
Cosmetic change to the checkboard() function output. Align the
output with the rest of initial output produced by U-Boot.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
The bi_boot_params must point to offset 0x100 in DRAM. Make it so.
Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek -
Cosmetic change to the print_cpuinfo() function output. Align the
output with the rest of initial output produced by U-Boot.Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek -
Add CPU function to register and initialize the dw_mmc SD controller.
This allows us to use the HPS SDMMC block.Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek -
Add function to initialize the EMAC blocks upon board startup.
The preprocessor guards against building on SoCFPGA-VT and against
SPL build are not needed as those are handled implicitly via both
SPL framework and the socfpga_cyclone5.h config file, which will
not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT.We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs.
Once there is hardware using both EMAC blocks, this ifdef will have
to go.Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek -
Add functions to reset the EMAC ethernet blocks. We cannot handle
two EMAC ethernet blocks yet, therefore the ifdefs. Once there is
hardware using both EMAC blocks, this ifdef will have to go.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
The timer reload value is a property of the timer hardware and there
is no reason for this to be configurable. Place this into the timer
driver just like on the other hardware.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Dinh Nguyen
Acked-by: Pavel Machek -
Make the SoCFPGA MMC stub pick clock via the clock manager
frequency accessors instead of hard-coding the frequency.Also fix calloc() misuse.
Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Dinh Nguyen -
Add the missing pieces from the reference clock code from Altera. This
puts the code on par with the Altera U-Boot fork for all but the SDRAM
self-refresh bits, which are not part of this patch.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Clean up the clock code definitions so they are aligned with mainline
standards. There are no functional changes in this patch.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Pull out functions to read frequency of Main clock VCO and
PLL clock VCO as the code is duplicated multiple times.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Dinh Nguyen
Acked-by: Pavel Machek -
Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel MachekV2: Fixed the L4 MP clock divider and synced the clock code with latest
rocketboards codebase (thanks Dinh for pointing this out) -
Add some stub defines, which are used by the clock code, but are
missing from the auto-generated header file for the SoCFPGA family.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Dinh Nguyen
Acked-by: Pavel Machek -
The inlining is done by GCC when needed, there is no need to do it
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint for the compiler. Scrub this hint.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Dinh Nguyen
Acked-by: Pavel Machek -
The bit definitions for clock manager are complete chaos. Implement
some basic logical order into them.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Clean up the system manager register definition and add the missing
register definitions in place.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel MachekV2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h
Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default) -
Sort the list of functional block addresses and fix indentation.
No functional change.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek
Acked-by: Chin Liang See -
Add base addresses for all subsystems as documented in the
Cyclone V HPS documentation.Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Chin Liang See -
…ic/drivers/net-20141006', 'topic/tools/mkimage-20141006' and 'topic/arm/cache-20141006' into HEAD
-
Add configuration for the write-allocate mode of L1 D-Cache on ARM.
This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA .Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel Machek -
Like many platforms, the Altera socfpga platform requires that the
preloader be "signed" in a certain way or the built-in boot ROM will
not boot the code.This change automatically creates an appropriately signed preloader
from an SPL image.The signed image includes a CRC which must, of course, be generated
with a CRC generator that the SoCFPGA boot ROM agrees with otherwise
the boot ROM will reject the image.Unfortunately the CRC used in this boot ROM is not the same as the
Adler CRC in lib/crc32.c. Indeed the Adler code is not technically a
CRC but is more correctly described as a checksum.Thus, the appropriate CRC generator is added to lib/ as crc32_alt.c.
Signed-off-by: Charles Manning
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Acked-by: Pavel MachekV2: - Zap unused constant
- Explicitly print an error message in case of error
- Rework the hdr_checksum() function to take the *header directly
instead of a plan buffer pointer -
Add a few new variables to make the cache handling less cryptic.
Add a variable for DMA and DATA descriptor start and end, so the
correctness of the code is easier to inspect.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Cc: Joe Hershberger
Acked-by: Pavel Machek
Acked-by: Chin Liang See -
Fix remaining cache alignment issues in the DWC Ethernet driver.
Please note that the cache handling in the driver is making the
code hideous and thus the next patch cleans that up. In order to
make this change reviewable though, the cleanup is split from it.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Cc: Joe Hershberger
Acked-by: Pavel Machek -
Old saying says that more than three exclamation marks in a row are
sign of mental disease. Cleanup micrel.c.Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Cc: Joe Hershberger
Acked-by: Chin Liang See -
Remove this symbol from configs, since it's unused.
Signed-off-by: Pavel Machek
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Cc: Joe Hershberger
Acked-by: Chin Liang See -
The DMA descriptors used by the DW MMC block must be aligned to cacheline
size, otherwise we are unable to properly flush/inval cache over them and
we get data corruption.The reason I chose this approach of expanding the structure is because
the driver allocates the descriptors in bulk. This approach does waste
space by inserting slop inbetween the descriptors, but it makes access
to the descriptors easy as the compiler does know the real size of the
structure. It also makes cache operations easy, since the size of the
structure is cache aligned and the structure start address is as well.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Albert Aribaud
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Pavel Machek
Cc: Pantelis Antoniou
Acked-by: Pavel Machek
